The Experts below are selected from a list of 51432 Experts worldwide ranked by ideXlab platform
Pehlivan İhsan - One of the best experts on this subject based on the ideXlab platform.
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High speed FPGA-based chaotic oscillator design
'Elsevier BV', 2019Co-Authors: Tuna Murat, Can Bülent Fidan, İsmail Koyuncu, Murat Alçın, Pehlivan İhsanAbstract:In this study, autonomous Lu-Chen (2002) chaotic system has been implemented on FPGA using Heun numerical algorithm in VHDL 32-bit IQ-Math Fixed-Point Number format for developing embedded chaos-based engineering applications. The core units like multiplier, adder and subtractor units, which are compatible with Fixed-Point Number standart used in FPGA-based design, have been created by IP CORE Generator that developed for Xilinx. The designed system has been simulated and synthesized for the Virtex-6 FPGA chip. The chip statistics obtained from Place&Route processing of FPGA-based system and the phase portraits of the results received from the outputs have been presented. The results obtained from FPGA-based Lu-Chen chaotic oscillator have been compared with the computer-based results and the accuracy of the digital circuit-based design has been certified with the successful results. The maximum operating frequency of designed FPGA-based Lu-Chen chaotic oscillator is 464.688 MHz. The performed FPGA-based Lu-Chen chaotic oscillator presents the highest operating frequency among the others in the literature. Besides, the design provides better results than the other 3D FPGA-based chaotic oscillator structures with respect to FPGA resource utilization. In addition, MSE and RMSE accuracy analyzes were performed on the designed chaotic oscillator. The design provides the highest operating frequency among the others in the literature. In addition, it presents better results than the alternatives with respect to FPGA resource utilization. For this reason, this study demonstrates that hardware-based design of Lu-Chen chaotic system can be used in various chaos-based embedded system applications including cryptography, secure communication and random Number generation. (C) 2019 Elsevier B.V. All rights reserved
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Real Time Hardware Implementation of the 3D Chaotic Oscillator which having Golden-Section Equilibra
'Institute of Electrical and Electronics Engineers (IEEE)', 2016Co-Authors: Tuna Murat, Can Bülent Fidan, İsmail Koyuncu, Pehlivan İhsanAbstract:In this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) Fixed-Point Number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the "Route&Place" processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with Fixed-Point Number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-Point standard
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Real Time Hardware Implementation of the 3D Chaotic Oscillator which having Golden-Section Equilibra
'Institute of Electrical and Electronics Engineers (IEEE)', 2016Co-Authors: Tuna Murat, Fidan, Can Bülent, Koyuncu İsmail, Pehlivan İhsanAbstract:24th Signal Processing and Communication Application Conference (SIU) -- MAY 16-19, 2016 -- Zonguldak, TURKEYTuna, Murat/0000-0003-3511-1336; FIDAN, CAN BULENT/0000-0001-5252-6301WOS: 000391250900304In this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) Fixed-Point Number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the "Route&Place" processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with Fixed-Point Number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-Point standard.IEEE, Bulent Ecevit Univ, Dept Elect & Elect Engn, Bulent Ecevit Univ, Dept Biomed Engn, Bulent Ecevit Univ, Dept Comp Eng
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Real time hardware implementation of the 3D chaotic oscillator which having golden-section equilibra
'Institute of Electrical and Electronics Engineers (IEEE)', 2016Co-Authors: Tuna Murat, Fidan, Can Bülent, Koyuncu İsmail, Pehlivan İhsanAbstract:In this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) Fixed-Point Number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the “Route&Place” processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with Fixed-Point Number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-Point standard.Bu çalışmada, son yıllarda literatüre sunulan altın oran denge noktalarına sahip, sürekli zamanlı, otonom, üç boyutlu bir kaotik sistem, FPGA üzerinde ilk defa ayrık zamanlı olarak gerçeklenmiştir. Yapılan tasarımda, üç boyutlu kaotik sistem, 32 bit IQ-Math (16I16Q) sabit noktalı sayı formatında, Heun algoritması kullanılarak VHDL dilinde kodlanmıştır. Tasarlanan sistem Xilinx ISE tasarım aracı kullanılarak Virtex-6 FPGA çipinde sentezlenmiş ve test edilmiştir. Test sonuçlarına göre FPGA-tabanlı yeni kaotik işaret üretecinin çalışma frekansı 406.736 MHz olarak belirlenmiştir. Ayrıca yeni kaotik osilatörün, Xilinx ISE tasarım aracı üzerinde yapılan “Route&Place” işleminin ardından, elde edilen çip istatistikleri ve performans sonuçları sunulmuştur. FPGA üzerinde sabit noktalı sayı formatıyla gerçekleştirilen kaotik osilatör tasarımının, kayan noktalı sayı standardına göre daha az çip donanımı kullandığı ve çalışma frekansının daha yüksek olduğu gösterilmiştir
Tuna Murat - One of the best experts on this subject based on the ideXlab platform.
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High speed FPGA-based chaotic oscillator design
'Elsevier BV', 2019Co-Authors: Tuna Murat, Can Bülent Fidan, İsmail Koyuncu, Murat Alçın, Pehlivan İhsanAbstract:In this study, autonomous Lu-Chen (2002) chaotic system has been implemented on FPGA using Heun numerical algorithm in VHDL 32-bit IQ-Math Fixed-Point Number format for developing embedded chaos-based engineering applications. The core units like multiplier, adder and subtractor units, which are compatible with Fixed-Point Number standart used in FPGA-based design, have been created by IP CORE Generator that developed for Xilinx. The designed system has been simulated and synthesized for the Virtex-6 FPGA chip. The chip statistics obtained from Place&Route processing of FPGA-based system and the phase portraits of the results received from the outputs have been presented. The results obtained from FPGA-based Lu-Chen chaotic oscillator have been compared with the computer-based results and the accuracy of the digital circuit-based design has been certified with the successful results. The maximum operating frequency of designed FPGA-based Lu-Chen chaotic oscillator is 464.688 MHz. The performed FPGA-based Lu-Chen chaotic oscillator presents the highest operating frequency among the others in the literature. Besides, the design provides better results than the other 3D FPGA-based chaotic oscillator structures with respect to FPGA resource utilization. In addition, MSE and RMSE accuracy analyzes were performed on the designed chaotic oscillator. The design provides the highest operating frequency among the others in the literature. In addition, it presents better results than the alternatives with respect to FPGA resource utilization. For this reason, this study demonstrates that hardware-based design of Lu-Chen chaotic system can be used in various chaos-based embedded system applications including cryptography, secure communication and random Number generation. (C) 2019 Elsevier B.V. All rights reserved
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Real Time Hardware Implementation of the 3D Chaotic Oscillator which having Golden-Section Equilibra
'Institute of Electrical and Electronics Engineers (IEEE)', 2016Co-Authors: Tuna Murat, Can Bülent Fidan, İsmail Koyuncu, Pehlivan İhsanAbstract:In this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) Fixed-Point Number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the "Route&Place" processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with Fixed-Point Number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-Point standard
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Real Time Hardware Implementation of the 3D Chaotic Oscillator which having Golden-Section Equilibra
'Institute of Electrical and Electronics Engineers (IEEE)', 2016Co-Authors: Tuna Murat, Fidan, Can Bülent, Koyuncu İsmail, Pehlivan İhsanAbstract:24th Signal Processing and Communication Application Conference (SIU) -- MAY 16-19, 2016 -- Zonguldak, TURKEYTuna, Murat/0000-0003-3511-1336; FIDAN, CAN BULENT/0000-0001-5252-6301WOS: 000391250900304In this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) Fixed-Point Number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the "Route&Place" processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with Fixed-Point Number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-Point standard.IEEE, Bulent Ecevit Univ, Dept Elect & Elect Engn, Bulent Ecevit Univ, Dept Biomed Engn, Bulent Ecevit Univ, Dept Comp Eng
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Real time hardware implementation of the 3D chaotic oscillator which having golden-section equilibra
'Institute of Electrical and Electronics Engineers (IEEE)', 2016Co-Authors: Tuna Murat, Fidan, Can Bülent, Koyuncu İsmail, Pehlivan İhsanAbstract:In this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) Fixed-Point Number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the “Route&Place” processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with Fixed-Point Number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-Point standard.Bu çalışmada, son yıllarda literatüre sunulan altın oran denge noktalarına sahip, sürekli zamanlı, otonom, üç boyutlu bir kaotik sistem, FPGA üzerinde ilk defa ayrık zamanlı olarak gerçeklenmiştir. Yapılan tasarımda, üç boyutlu kaotik sistem, 32 bit IQ-Math (16I16Q) sabit noktalı sayı formatında, Heun algoritması kullanılarak VHDL dilinde kodlanmıştır. Tasarlanan sistem Xilinx ISE tasarım aracı kullanılarak Virtex-6 FPGA çipinde sentezlenmiş ve test edilmiştir. Test sonuçlarına göre FPGA-tabanlı yeni kaotik işaret üretecinin çalışma frekansı 406.736 MHz olarak belirlenmiştir. Ayrıca yeni kaotik osilatörün, Xilinx ISE tasarım aracı üzerinde yapılan “Route&Place” işleminin ardından, elde edilen çip istatistikleri ve performans sonuçları sunulmuştur. FPGA üzerinde sabit noktalı sayı formatıyla gerçekleştirilen kaotik osilatör tasarımının, kayan noktalı sayı standardına göre daha az çip donanımı kullandığı ve çalışma frekansının daha yüksek olduğu gösterilmiştir
İsmail Koyuncu - One of the best experts on this subject based on the ideXlab platform.
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High speed FPGA-based chaotic oscillator design
Microprocessors and Microsystems, 2019Co-Authors: Murat Tuna, Can Bülent Fidan, İsmail Koyuncu, Murat Alçın, Ihsan PehlivanAbstract:Abstract In this study, autonomous Lu-Chen (2002) chaotic system has been implemented on FPGA using Heun numerical algorithm in VHDL 32-bit IQ-Math Fixed-Point Number format for developing embedded chaos-based engineering applications. The core units like multiplier, adder and subtractor units, which are compatible with Fixed-Point Number standart used in FPGA-based design, have been created by IP CORE Generator that developed for Xilinx. The designed system has been simulated and synthesized for the Virtex–6 FPGA chip. The chip statistics obtained from Place&Route processing of FPGA-based system and the phase portraits of the results received from the outputs have been presented. The results obtained from FPGA-based Lu-Chen chaotic oscillator have been compared with the computer-based results and the accuracy of the digital circuit-based design has been certified with the successful results. The maximum operating frequency of designed FPGA-based Lu-Chen chaotic oscillator is 464.688 MHz. The performed FPGA-based Lu-Chen chaotic oscillator presents the highest operating frequency among the others in the literature. Besides, the design provides better results than the other 3D FPGA-based chaotic oscillator structures with respect to FPGA resource utilization. In addition, MSE and RMSE accuracy analyzes were performed on the designed chaotic oscillator. The design provides the highest operating frequency among the others in the literature. In addition, it presents better results than the alternatives with respect to FPGA resource utilization. For this reason, this study demonstrates that hardware-based design of Lu-Chen chaotic system can be used in various chaos-based embedded system applications including cryptography, secure communication and random Number generation.
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High speed FPGA-based chaotic oscillator design
'Elsevier BV', 2019Co-Authors: Tuna Murat, Can Bülent Fidan, İsmail Koyuncu, Murat Alçın, Pehlivan İhsanAbstract:In this study, autonomous Lu-Chen (2002) chaotic system has been implemented on FPGA using Heun numerical algorithm in VHDL 32-bit IQ-Math Fixed-Point Number format for developing embedded chaos-based engineering applications. The core units like multiplier, adder and subtractor units, which are compatible with Fixed-Point Number standart used in FPGA-based design, have been created by IP CORE Generator that developed for Xilinx. The designed system has been simulated and synthesized for the Virtex-6 FPGA chip. The chip statistics obtained from Place&Route processing of FPGA-based system and the phase portraits of the results received from the outputs have been presented. The results obtained from FPGA-based Lu-Chen chaotic oscillator have been compared with the computer-based results and the accuracy of the digital circuit-based design has been certified with the successful results. The maximum operating frequency of designed FPGA-based Lu-Chen chaotic oscillator is 464.688 MHz. The performed FPGA-based Lu-Chen chaotic oscillator presents the highest operating frequency among the others in the literature. Besides, the design provides better results than the other 3D FPGA-based chaotic oscillator structures with respect to FPGA resource utilization. In addition, MSE and RMSE accuracy analyzes were performed on the designed chaotic oscillator. The design provides the highest operating frequency among the others in the literature. In addition, it presents better results than the alternatives with respect to FPGA resource utilization. For this reason, this study demonstrates that hardware-based design of Lu-Chen chaotic system can be used in various chaos-based embedded system applications including cryptography, secure communication and random Number generation. (C) 2019 Elsevier B.V. All rights reserved
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Real Time Hardware Implementation of the 3D Chaotic Oscillator which having Golden-Section Equilibra
'Institute of Electrical and Electronics Engineers (IEEE)', 2016Co-Authors: Tuna Murat, Can Bülent Fidan, İsmail Koyuncu, Pehlivan İhsanAbstract:In this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) Fixed-Point Number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the "Route&Place" processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with Fixed-Point Number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-Point standard
Can Bülent Fidan - One of the best experts on this subject based on the ideXlab platform.
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High speed FPGA-based chaotic oscillator design
Microprocessors and Microsystems, 2019Co-Authors: Murat Tuna, Can Bülent Fidan, İsmail Koyuncu, Murat Alçın, Ihsan PehlivanAbstract:Abstract In this study, autonomous Lu-Chen (2002) chaotic system has been implemented on FPGA using Heun numerical algorithm in VHDL 32-bit IQ-Math Fixed-Point Number format for developing embedded chaos-based engineering applications. The core units like multiplier, adder and subtractor units, which are compatible with Fixed-Point Number standart used in FPGA-based design, have been created by IP CORE Generator that developed for Xilinx. The designed system has been simulated and synthesized for the Virtex–6 FPGA chip. The chip statistics obtained from Place&Route processing of FPGA-based system and the phase portraits of the results received from the outputs have been presented. The results obtained from FPGA-based Lu-Chen chaotic oscillator have been compared with the computer-based results and the accuracy of the digital circuit-based design has been certified with the successful results. The maximum operating frequency of designed FPGA-based Lu-Chen chaotic oscillator is 464.688 MHz. The performed FPGA-based Lu-Chen chaotic oscillator presents the highest operating frequency among the others in the literature. Besides, the design provides better results than the other 3D FPGA-based chaotic oscillator structures with respect to FPGA resource utilization. In addition, MSE and RMSE accuracy analyzes were performed on the designed chaotic oscillator. The design provides the highest operating frequency among the others in the literature. In addition, it presents better results than the alternatives with respect to FPGA resource utilization. For this reason, this study demonstrates that hardware-based design of Lu-Chen chaotic system can be used in various chaos-based embedded system applications including cryptography, secure communication and random Number generation.
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High speed FPGA-based chaotic oscillator design
'Elsevier BV', 2019Co-Authors: Tuna Murat, Can Bülent Fidan, İsmail Koyuncu, Murat Alçın, Pehlivan İhsanAbstract:In this study, autonomous Lu-Chen (2002) chaotic system has been implemented on FPGA using Heun numerical algorithm in VHDL 32-bit IQ-Math Fixed-Point Number format for developing embedded chaos-based engineering applications. The core units like multiplier, adder and subtractor units, which are compatible with Fixed-Point Number standart used in FPGA-based design, have been created by IP CORE Generator that developed for Xilinx. The designed system has been simulated and synthesized for the Virtex-6 FPGA chip. The chip statistics obtained from Place&Route processing of FPGA-based system and the phase portraits of the results received from the outputs have been presented. The results obtained from FPGA-based Lu-Chen chaotic oscillator have been compared with the computer-based results and the accuracy of the digital circuit-based design has been certified with the successful results. The maximum operating frequency of designed FPGA-based Lu-Chen chaotic oscillator is 464.688 MHz. The performed FPGA-based Lu-Chen chaotic oscillator presents the highest operating frequency among the others in the literature. Besides, the design provides better results than the other 3D FPGA-based chaotic oscillator structures with respect to FPGA resource utilization. In addition, MSE and RMSE accuracy analyzes were performed on the designed chaotic oscillator. The design provides the highest operating frequency among the others in the literature. In addition, it presents better results than the alternatives with respect to FPGA resource utilization. For this reason, this study demonstrates that hardware-based design of Lu-Chen chaotic system can be used in various chaos-based embedded system applications including cryptography, secure communication and random Number generation. (C) 2019 Elsevier B.V. All rights reserved
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Real Time Hardware Implementation of the 3D Chaotic Oscillator which having Golden-Section Equilibra
'Institute of Electrical and Electronics Engineers (IEEE)', 2016Co-Authors: Tuna Murat, Can Bülent Fidan, İsmail Koyuncu, Pehlivan İhsanAbstract:In this study, the continuous-time, autonomous, 3D chaotic system having golden-section equilibra which is recently presented in the literature is implemented firstly as discrete time on an FPGA. In this design, the 3D chaotic system was programmed in 32-bit IQ-Math (16I-16Q) Fixed-Point Number format using VHDL and Heun algorithm. The designed system has been synthesized and tested, using Xilinx ISE design tool, on Virtex-6 FPGA chip. According to the test results, operation frequency of the FPGA-based new chaotic signal generator is certain as 406.736MHz. In addition, chip statistics and performance results of the new chaotic oscillator are presented after the "Route&Place" processes performed on Xilinx ISE design tool. The chaotic oscillator design realized with Fixed-Point Number format on FPGA has been shown to be use lesser chip hardware and higher operating frequency compared to the floating-Point standard
Ibrahim Khalil - One of the best experts on this subject based on the ideXlab platform.
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design and implementation of a secure cloud based billing model for smart meters as an internet of things using homomorphic cryptography
Future Generation Computer Systems, 2017Co-Authors: Vu Mai, Ibrahim KhalilAbstract:Smart grids introduce many outstanding security and privacy issues, especially when smart meters are connected to public networks, creating an Internet of things in which customer usage data is frequently exchanged and processed in large volumes. In this research, we propose a cloud-based data storage and processing model with the ability to preserve user privacy and confidentiality of smart meter data in a smart grid. This goal is achieved by encrypting smart meter data before storage on the cloud using a homomorphic asymmetric key cryptosystem. By applying the homomorphic feature of the cryptographic technique, we propose methods to allow most of the computing works of calculating customer invoices based on total electricity consumption to be done directly on encrypted data by the cloud. One of the outstanding features in our model is the aggregation of encrypted smart meter readings using Fixed-Point Number arithmetic. To test the feasibility of our model, we conducted many experiments to estimate the Number of homomorphic additions to be performed by the cloud and the computation time in different billing periods using data from the Smart project, in which smart grid readings were continuously collected from different households in every second within two months and electricity usage data collected every minute from 400 anonymous houses in one day. We also propose a parallel version of our billing algorithm to utilize the processing capability of multi-core processors in cloud servers so that computation time is reduced significantly compared to using our sequential algorithm. Our research works and experiments demonstrate clearly how cloud services can strengthen the security, privacy and efficiency of privacy-sensitive data frequently exchanged and processed in an Internet of things where smart meters communicate directly with public networks. A cloud-based smart meter data processing model preserving user confidentiality.Aggregation of encrypted smart meter readings with encrypted Fixed-Point Number.Calculating the computation time of encrypted additions performed on cloud.A parallel version of our billing algorithm using multi-core processors on cloud.