The Experts below are selected from a list of 276 Experts worldwide ranked by ideXlab platform
Y Manoli - One of the best experts on this subject based on the ideXlab platform.
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a multibit continuous time sigma delta modulator with successive approximation quantizer
International Symposium on Circuits and Systems, 2006Co-Authors: L Samid, Y ManoliAbstract:This paper discusses the design of a multibit sigma-delta modulator using a continuous time (CT) loop filter and a successive approximation (SA) A/D Converter as multibit quantizer instead of the usual Flash Converter. This results in reduced circuit complexity as well as lower power dissipation and area. Measured results of a second order CT modulator with three bits quantizer show 58 dB SNR and 120 /spl mu/W power dissipation with an OSR of 16 and a power supply equal to 1.5 V.
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ISCAS - A multibit continuous time sigma delta modulator with successive-approximation quantizer
2006 IEEE International Symposium on Circuits and Systems, 1Co-Authors: L Samid, Y ManoliAbstract:This paper discusses the design of a multibit sigma-delta modulator using a continuous time (CT) loop filter and a successive approximation (SA) A/D Converter as multibit quantizer instead of the usual Flash Converter. This results in reduced circuit complexity as well as lower power dissipation and area. Measured results of a second order CT modulator with three bits quantizer show 58 dB SNR and 120 /spl mu/W power dissipation with an OSR of 16 and a power supply equal to 1.5 V.
A. Xotta - One of the best experts on this subject based on the ideXlab platform.
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An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling $SigmaDelta$ Modulator and a Flash Converter
IEEE Transactions on Circuits and Systems I: Regular Papers, 2006Co-Authors: Andrea Gerosa, Andrea Bevilacqua, A. Xotta, Andrea NevianiAbstract:This work proposes an architecture for an analog-to-digital Converter intended for a multimode wireless receiver. The architecture is based on the cascade of a single-bit 2-1 sigma-delta modulator and a 4-bit Flash Converter. Furthermore such an architecture is mapped in a modular implementation, which allows to easily reconfigure modulator order, oversampling ratio and equivalent number of bits of the internal quantizer. As a consequence, the proposed Converter can fulfil the requirement of a wide range of standards: Global System for Mobile Communications (GSM), Bluetooth, universal mobile telecommunications system (UMTS), and wireless local area network (WLAN)a. The paper discusses extensively the effects of circuit nonidealities on the Converter performance, in order to single out the most suited setup for the programmable parameters and to demonstrate the practical feasibility of the proposed system. The Converter figures of merit have been quantified by means of transistor-level and behavioral simulations: the achieved dynamic range is 85, 72, 62, and 59 dB for GSM, Bluetooth, UMTS, and WLANa, respectively. The corresponding power consumption is 4.6, 5.5, 7.4, and 18.9 mW
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ISCAS - An optimal architecture for a multimode ADC, based on the cascade of a /spl Sigma//spl Delta/ modulator and a Flash Converter
2006 IEEE International Symposium on Circuits and Systems, 1Co-Authors: Andrea Gerosa, Andrea Bevilacqua, Andrea Neviani, A. XottaAbstract:This work proposes an architecture for a multimode ADC. The architecture is based on the cascade of a single-bit 2-1 /spl Sigma//spl Delta/ modulator and a 4-bit Flash Converter. Furthermore such an architecture is mapped in a modular implementation, which allows to easily reconfigure modulator order, oversampling ratio and equivalent number of bits of the internal quantizer. As a consequence the proposed Converter can fulfil the requirement of a wide range of standards: GSM, Bluetooth, UMTS and WLANa. The achieved dynamic range is 85dB, 72dB, 62dB and 59dB for GSM, Bluetooth, UMTS and WLANa, respectively. The corresponding power consumption is 4.6mW, 5.5mW, 7.4mW and 18.9mW.
Andrea Neviani - One of the best experts on this subject based on the ideXlab platform.
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An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling $SigmaDelta$ Modulator and a Flash Converter
IEEE Transactions on Circuits and Systems I: Regular Papers, 2006Co-Authors: Andrea Gerosa, Andrea Bevilacqua, A. Xotta, Andrea NevianiAbstract:This work proposes an architecture for an analog-to-digital Converter intended for a multimode wireless receiver. The architecture is based on the cascade of a single-bit 2-1 sigma-delta modulator and a 4-bit Flash Converter. Furthermore such an architecture is mapped in a modular implementation, which allows to easily reconfigure modulator order, oversampling ratio and equivalent number of bits of the internal quantizer. As a consequence, the proposed Converter can fulfil the requirement of a wide range of standards: Global System for Mobile Communications (GSM), Bluetooth, universal mobile telecommunications system (UMTS), and wireless local area network (WLAN)a. The paper discusses extensively the effects of circuit nonidealities on the Converter performance, in order to single out the most suited setup for the programmable parameters and to demonstrate the practical feasibility of the proposed system. The Converter figures of merit have been quantified by means of transistor-level and behavioral simulations: the achieved dynamic range is 85, 72, 62, and 59 dB for GSM, Bluetooth, UMTS, and WLANa, respectively. The corresponding power consumption is 4.6, 5.5, 7.4, and 18.9 mW
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ISCAS - An optimal architecture for a multimode ADC, based on the cascade of a /spl Sigma//spl Delta/ modulator and a Flash Converter
2006 IEEE International Symposium on Circuits and Systems, 1Co-Authors: Andrea Gerosa, Andrea Bevilacqua, Andrea Neviani, A. XottaAbstract:This work proposes an architecture for a multimode ADC. The architecture is based on the cascade of a single-bit 2-1 /spl Sigma//spl Delta/ modulator and a 4-bit Flash Converter. Furthermore such an architecture is mapped in a modular implementation, which allows to easily reconfigure modulator order, oversampling ratio and equivalent number of bits of the internal quantizer. As a consequence the proposed Converter can fulfil the requirement of a wide range of standards: GSM, Bluetooth, UMTS and WLANa. The achieved dynamic range is 85dB, 72dB, 62dB and 59dB for GSM, Bluetooth, UMTS and WLANa, respectively. The corresponding power consumption is 4.6mW, 5.5mW, 7.4mW and 18.9mW.
Andrea Gerosa - One of the best experts on this subject based on the ideXlab platform.
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An A/D Converter for Multimode Wireless Receivers, Based on the Cascade of a Double-Sampling $SigmaDelta$ Modulator and a Flash Converter
IEEE Transactions on Circuits and Systems I: Regular Papers, 2006Co-Authors: Andrea Gerosa, Andrea Bevilacqua, A. Xotta, Andrea NevianiAbstract:This work proposes an architecture for an analog-to-digital Converter intended for a multimode wireless receiver. The architecture is based on the cascade of a single-bit 2-1 sigma-delta modulator and a 4-bit Flash Converter. Furthermore such an architecture is mapped in a modular implementation, which allows to easily reconfigure modulator order, oversampling ratio and equivalent number of bits of the internal quantizer. As a consequence, the proposed Converter can fulfil the requirement of a wide range of standards: Global System for Mobile Communications (GSM), Bluetooth, universal mobile telecommunications system (UMTS), and wireless local area network (WLAN)a. The paper discusses extensively the effects of circuit nonidealities on the Converter performance, in order to single out the most suited setup for the programmable parameters and to demonstrate the practical feasibility of the proposed system. The Converter figures of merit have been quantified by means of transistor-level and behavioral simulations: the achieved dynamic range is 85, 72, 62, and 59 dB for GSM, Bluetooth, UMTS, and WLANa, respectively. The corresponding power consumption is 4.6, 5.5, 7.4, and 18.9 mW
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ISCAS - An optimal architecture for a multimode ADC, based on the cascade of a /spl Sigma//spl Delta/ modulator and a Flash Converter
2006 IEEE International Symposium on Circuits and Systems, 1Co-Authors: Andrea Gerosa, Andrea Bevilacqua, Andrea Neviani, A. XottaAbstract:This work proposes an architecture for a multimode ADC. The architecture is based on the cascade of a single-bit 2-1 /spl Sigma//spl Delta/ modulator and a 4-bit Flash Converter. Furthermore such an architecture is mapped in a modular implementation, which allows to easily reconfigure modulator order, oversampling ratio and equivalent number of bits of the internal quantizer. As a consequence the proposed Converter can fulfil the requirement of a wide range of standards: GSM, Bluetooth, UMTS and WLANa. The achieved dynamic range is 85dB, 72dB, 62dB and 59dB for GSM, Bluetooth, UMTS and WLANa, respectively. The corresponding power consumption is 4.6mW, 5.5mW, 7.4mW and 18.9mW.
L Samid - One of the best experts on this subject based on the ideXlab platform.
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a multibit continuous time sigma delta modulator with successive approximation quantizer
International Symposium on Circuits and Systems, 2006Co-Authors: L Samid, Y ManoliAbstract:This paper discusses the design of a multibit sigma-delta modulator using a continuous time (CT) loop filter and a successive approximation (SA) A/D Converter as multibit quantizer instead of the usual Flash Converter. This results in reduced circuit complexity as well as lower power dissipation and area. Measured results of a second order CT modulator with three bits quantizer show 58 dB SNR and 120 /spl mu/W power dissipation with an OSR of 16 and a power supply equal to 1.5 V.
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ISCAS - A multibit continuous time sigma delta modulator with successive-approximation quantizer
2006 IEEE International Symposium on Circuits and Systems, 1Co-Authors: L Samid, Y ManoliAbstract:This paper discusses the design of a multibit sigma-delta modulator using a continuous time (CT) loop filter and a successive approximation (SA) A/D Converter as multibit quantizer instead of the usual Flash Converter. This results in reduced circuit complexity as well as lower power dissipation and area. Measured results of a second order CT modulator with three bits quantizer show 58 dB SNR and 120 /spl mu/W power dissipation with an OSR of 16 and a power supply equal to 1.5 V.