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Taesun Chung - One of the best experts on this subject based on the ideXlab platform.

  • Hierarchical Request-Size-Aware Flash Translation Layer Based on Page-Level Mapping
    Journal of Circuits Systems and Computers, 2019
    Co-Authors: Joon-yong Paik, Taesun Chung
    Abstract:

    Owing to the increasing Internet population, there has been an explosion in the amount of digital data generated and also an increase in data complexity. This trend is called big data paradigm. As the Internet of Things (IoT) takes center stage, the growth of data will continue to increase. Therefore, the demand for mass storage devices that have high access speed is increasing. Industry has been paying attention to Flash memories that can process large amounts of data at high speed. It will be a good alternative for storing and processing ever-increasing amounts of data because of low power consumption, high shock resistance, portability and fast access speed. However, the write speed is about 10–20 times slower than the read speed in Flash memory. In addition, write operations are not allowed to be performed with in-place updates. Garbage collection mechanism is proposed in order to solve the problem incurred by the not-in-place update property of write operations. However, garbage collection mechanism unavoidably causes overhead of additional internal operations, which leads to performance degradation. In this paper, to prevent performance degradation caused by garbage collection, we propose a request-size-aware Flash Translation Layer (RSaFTL) and a hierarchical request-size-aware Flash Translation Layer (HiRSaFTL). They are designed based on page-level address Translation. In RSaFTL and HiRSaFTL, page-sized data with high temporal locality cluster into a special area called active blocks by exploiting the property of realistic traces. As a result of the experiments, RSaFTL and HiRSaFTL reduce the number of pages migrated during garbage collections by up to 17.9% and 21.3%, respectively, compared with pure page-level Flash transition Layer.

  • CSE/EUC/DCABES - Request-Size Aware Flash Translation Layer Based on Page-Level Mapping
    2016 IEEE Intl Conference on Computational Science and Engineering (CSE) and IEEE Intl Conference on Embedded and Ubiquitous Computing (EUC) and 15th , 2016
    Co-Authors: Joon-young Paik, Taesun Chung
    Abstract:

    As more and more Flash memory technologies quickly improve, NAND Flash memory storage system has become more and more used as a non-volatile storage for embedded applications such as smart phones, smart watch, digital camera and so on. The software Layer called Flash Translation Layer (FTL) becomes more important since it is a key factor in the overall Flash memory system performance. However, the Flash storage system does not perform well because of their hardware feature and the cost of garbage collection. To overcome this limitations, in this paper we provide a novel page mapping scheme named Request-Size aware Flash Translation Layer (RSaFTL) based on the page-level mapping algorithm. Our FTL is designed to reduce garbage collection overhead by using characteristics of overwriting one-page-unit data in Flash memory. Experimental results show that RSaFTL outperforms the pure page mapping scheme by up to 29.4% on write-intensive workload with no addition RAM resource.

  • Request-Size Aware Flash Translation Layer Based on Page-Level Mapping
    2016 IEEE Intl Conference on Computational Science and Engineering (CSE) and IEEE Intl Conference on Embedded and Ubiquitous Computing (EUC) and 15th , 2016
    Co-Authors: Joon-young Paik, Taesun Chung
    Abstract:

    As more and more Flash memory technologies quickly improve, NAND Flash memory storage system has become more and more used as a non-volatile storage for embedded applications such as smart phones, smart watch, digital camera and so on. The software Layer called Flash Translation Layer (FTL) becomes more important since it is a key factor in the overall Flash memory system performance. However, the Flash storage system does not perform well because of their hardware feature and the cost of garbage collection. To overcome this limitations, in this paper we provide a novel page mapping scheme named Request-Size aware Flash Translation Layer (RSaFTL) based on the page-level mapping algorithm. Our FTL is designed to reduce garbage collection overhead by using characteristics of overwriting one-page-unit data in Flash memory. Experimental results show that RSaFTL outperforms the pure page mapping scheme by up to 29.4% on write-intensive workload with no addition RAM resource.

  • an efficient Flash Translation Layer for large block nand Flash devices
    Journal of Circuits Systems and Computers, 2015
    Co-Authors: Taesun Chung, Dongjoo Park
    Abstract:

    Recently, Flash memory is widely used as a non-volatile storage for embedded applications such as smart phones, MP3 pLayers, digital cameras and so on. The software Layer called Flash Translation Layer (FTL) becomes more important since it is a key factor in the overall Flash memory system performance. Many researchers have proposed FTL algorithms for small block Flash memory in which the size of a physical page of Flash memory is equivalent to the size of a data sector of the file system. However, major Flash vendors have now produced large block Flash memory in which the size of a physical page is larger than the file system's data sector size. Since large block Flash memory has new features, designing FTL algorithms specialized to large block Flash memory is a challenging issue. In this paper, we provide an efficient FTL named LSTAFF* for large block Flash memory. LSTAFF* is designed to achieve better performance by using characteristics of large block Flash memory and to provide safety by abiding by restrictions of large block Flash memory. Experimental results show that LSTAFF* outperforms existing algorithms on a large block Flash memory.

  • Fast responsive Flash Translation Layer for smart devices
    IEEE Transactions on Consumer Electronics, 2014
    Co-Authors: Se Jin Kwon, Taesun Chung
    Abstract:

    The Flash Translation Layer design of smart devices differs from that of traditional storages, because smart devices have frequent power-offs and limited resources. These unique features of smart devices generate inconsistent response times and performance degradation. This paper proposes a new FTL algorithm called the "Fast Responsive Flash Translation Layer (FFTL)" for smart devices. FFTL avoids frequent merge operations by first executing a cleaning policy and provides a faster response time than superblocklevel associativity algorithms by balancing the associativity of each log block. Furthermore, FFTL utilizes all the sectors within each page, thereby reducing the number of write operations. According to the experimental results, it outperforms MCSplit, Superblock, and MAST in terms of the average response time and number of operations.

Myungjin Jung - One of the best experts on this subject based on the ideXlab platform.

  • staff state transition applied fast Flash Translation Layer
    Automation Robotics and Control Systems, 2004
    Co-Authors: Taesun Chung, Stein Park, Myungjin Jung
    Abstract:

    Recently, Flash memory is widely used in embedded applications since it has strong points: non-volatility, fast access speed, shock resistance, and low power consumption. However, due to its hardware characteristics, it requires a software Layer called FTL (Flash Translation Layer). The main functionality of FTL is to convert logical addresses from the host to physical addresses of Flash memory. We present a new FTL algorithm called STAFF (State Transition Applied Fast Flash Translation Layer). Compared to the previous FTL algorithms, STAFF shows higher performance and requires less memory. We provide performance results based on our implementation of STAFF and previous FTL algorithms.

  • ARCS - STAFF: State Transition Applied Fast Flash Translation Layer
    Lecture Notes in Computer Science, 2004
    Co-Authors: Taesun Chung, Stein Park, Myungjin Jung
    Abstract:

    Recently, Flash memory is widely used in embedded applications since it has strong points: non-volatility, fast access speed, shock resistance, and low power consumption. However, due to its hardware characteristics, it requires a software Layer called FTL (Flash Translation Layer). The main functionality of FTL is to convert logical addresses from the host to physical addresses of Flash memory. We present a new FTL algorithm called STAFF (State Transition Applied Fast Flash Translation Layer). Compared to the previous FTL algorithms, STAFF shows higher performance and requires less memory. We provide performance results based on our implementation of STAFF and previous FTL algorithms.

David H C Du - One of the best experts on this subject based on the ideXlab platform.

  • A Workload-Aware Adaptive Hybrid Flash Translation Layer with an Efficient Caching Strategy
    2011 IEEE 19th Annual International Symposium on Modelling Analysis and Simulation of Computer and Telecommunication Systems, 2011
    Co-Authors: Dongchul Park, Biplob Debnath, David H C Du
    Abstract:

    In this paper, we propose a Convertible Flash Translation Layer (CFTL) for NAND Flash-based storage systems. CFTL is a novel hybrid Flash Translation Layer adaptive to workloads so that it can dynamically switch its mapping scheme to either a page level mapping or a block level mapping scheme to fully exploit the benefits of them. Moreover, we propose an efficient caching strategy to further improve the CFTL performance. Consequently, both the convertible feature and the caching strategy empower CFTL to achieve good read performance as well as good write performance. Our experimental evaluation with various realistic workloads demonstrates that CFTL outweighs other FTL schemes. In particular, our new caching strategy remarkably improves cache hit ratios, by an average of 245%, and exhibits much higher hit ratios especially for randomly read intensive workloads.

  • MASCOTS - A Workload-Aware Adaptive Hybrid Flash Translation Layer with an Efficient Caching Strategy
    2011 IEEE 19th Annual International Symposium on Modelling Analysis and Simulation of Computer and Telecommunication Systems, 2011
    Co-Authors: Dongchul Park, Biplob Debnath, David H C Du
    Abstract:

    In this paper, we propose a Convertible Flash Translation Layer (CFTL) for NAND Flash-based storage systems. CFTL is a novel hybrid Flash Translation Layer adaptive to workloads so that it can dynamically switch its mapping scheme to either a page level mapping or a block level mapping scheme to fully exploit the benefits of them. Moreover, we propose an efficient caching strategy to further improve the CFTL performance. Consequently, both the convertible feature and the caching strategy empower CFTL to achieve good read performance as well as good write performance. Our experimental evaluation with various realistic workloads demonstrates that CFTL outweighs other FTL schemes. In particular, our new caching strategy remarkably improves cache hit ratios, by an average of 245%, and exhibits much higher hit ratios especially for randomly read intensive workloads.

  • cftl a convertible Flash Translation Layer adaptive to data access patterns
    Measurement and Modeling of Computer Systems, 2010
    Co-Authors: Dongchul Park, Biplob Debnath, David H C Du
    Abstract:

    The Flash Translation Layer (FTL) is a software/hardware in terface inside NAND Flash memory. Since FTL has a critical impact on the performance of NAND Flash-based devices, a variety of FTL schemes have been proposed to improve their performance. In this paper, we propose a novel hybrid FTL scheme named Convertible Flash Translation Layer (CFTL). Unlike other existing FTLs using static address mapping schemes, CFTL is adaptive to data access patterns so that it can dynamically switch its mapping scheme to either a read-optimized or a write-optimized mapping scheme. In addition to this convertible scheme, we propose an efficient caching strategy to further improve the CFTL performance with only a simple hint. Consequently, both the convertible feature and the caching strategy empower CFTL to achieve good read performance as well as good write performance.

  • SIGMETRICS - CFTL: a convertible Flash Translation Layer adaptive to data access patterns
    Proceedings of the ACM SIGMETRICS international conference on Measurement and modeling of computer systems - SIGMETRICS '10, 2010
    Co-Authors: Dongchul Park, Biplob Debnath, David H C Du
    Abstract:

    The Flash Translation Layer (FTL) is a software/hardware in terface inside NAND Flash memory. Since FTL has a critical impact on the performance of NAND Flash-based devices, a variety of FTL schemes have been proposed to improve their performance. In this paper, we propose a novel hybrid FTL scheme named Convertible Flash Translation Layer (CFTL). Unlike other existing FTLs using static address mapping schemes, CFTL is adaptive to data access patterns so that it can dynamically switch its mapping scheme to either a read-optimized or a write-optimized mapping scheme. In addition to this convertible scheme, we propose an efficient caching strategy to further improve the CFTL performance with only a simple hint. Consequently, both the convertible feature and the caching strategy empower CFTL to achieve good read performance as well as good write performance.

Zili Shao - One of the best experts on this subject based on the ideXlab platform.

  • A Real-Time Flash Translation Layer for NAND Flash Memory Storage Systems
    IEEE Transactions on Multi-Scale Computing Systems, 2016
    Co-Authors: Yi Wang, Zili Shao, Renhai Chen, Qixin Wang, Shuai Li, Laurence T. Yang
    Abstract:

    NAND Flash memory is widely used in both hard real-time and soft real-time systems because of its unique properties, such as non-volatility, low power consumption, and fast access time. However, due to the variable garbage collection latency, the response time becomes unpredictable when multiple I/O requests are issued from the file system to Flash media. In NAND Flash memory storage systems, Flash Translation Layer (FTL) is a typical software module to handle the I/O requests and manage NAND Flash memory. Most of existing FTL schemes focus on improving average response time but worst-case response time remains an open problem. This paper proposes a real-time Flash Translation Layer (RFTL) scheme to evenly distribute garbage collection time-cost, so as to guarantee a near optimum worst-case response time. This is achieved by using a new hybrid-level address mapping approach, which can provide guaranteed physical space to serve requests in any time period. Moreover, we propose a distributed garbage collection policy that enables RFTL to reclaim the space and serve the requests simultaneously. We conduct a set of experiments on a real hardware platform. Both the proposed scheme and other representative FTL schemes have been implemented in the hardware evaluation board. Experimental results show that our scheme improves worst-case response time by 41.51 percent and average response time by 88.85 percent.

  • Real-Time Flash Translation Layer for NAND Flash Memory Storage Systems
    2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium, 2012
    Co-Authors: Yi Wang, Zili Shao
    Abstract:

    Due to the variable garbage collection latency, NAND Flash memory storage systems may suffer long system response time, especially when the Flash memory is close to be full. Most of existing Flash Translation Layer (FTL) schemes focus on improving the average response time but ignore to provide a desirable worst case response time upper bound. This paper proposes a Real-time Flash Translation Layer (RFTL) scheme to hide the long garbage collection latency while satisfying a worst case response time upper bound that achieves an ideal case. We achieve this by using a distributed partial garbage collection policy that enables RFTL to reclaim the space and to serve the write requests simultaneously. A new block-level address mapping approach is designed to guarantee enough free space to serve the write request arriving at any time period. Experimental results show that our scheme improves both the worst case system response time and the average system response time compared with previous work.

  • IEEE Real-Time and Embedded Technology and Applications Symposium - Real-Time Flash Translation Layer for NAND Flash Memory Storage Systems
    2012 IEEE 18th Real Time and Embedded Technology and Applications Symposium, 2012
    Co-Authors: Yi Wang, Zili Shao
    Abstract:

    Due to the variable garbage collection latency, NAND Flash memory storage systems may suffer long system response time, especially when the Flash memory is close to be full. Most of existing Flash Translation Layer (FTL) schemes focus on improving the average response time but ignore to provide a desirable worst case response time upper bound. This paper proposes a Real-time Flash Translation Layer (RFTL) scheme to hide the long garbage collection latency while satisfying a worst case response time upper bound that achieves an ideal case. We achieve this by using a distributed partial garbage collection policy that enables RFTL to reclaim the space and to serve the write requests simultaneously. A new block-level address mapping approach is designed to guarantee enough free space to serve the write request arriving at any time period. Experimental results show that our scheme improves both the worst case system response time and the average system response time compared with previous work.

  • MNFTL: An efficient Flash Translation Layer for MLC NAND Flash memory storage systems
    2011 48th ACM EDAC IEEE Design Automation Conference (DAC), 2011
    Co-Authors: Yi Wang, Zili Shao, Yong Guan
    Abstract:

    The new write constraints of multi-level cell (MLC) NAND Flash memory make most of the existing Flash Translation Layer (FTL) schemes inefficient or inapplicable. In this paper, we solve several fundamental problems in the design of MLC Flash Translation Layer. The objective is to reduce the garbage collection overhead so as to reduce the average system response time. We make the key observation that the valid page copy is the essential garbage collection overhead. Based on this observation, we propose two approaches, namely, concentrated mapping and postponed reclamation, to effective reduce the valid page copies. We conduct experiments on a set of benchmarks from both the real world and synthetic traces. The experimental results show that our scheme can achieve a significant reduction in the average system response time compared with the previous work.

  • DAC - MNFTL: an efficient Flash Translation Layer for MLC NAND Flash memory storage systems
    Proceedings of the 48th Design Automation Conference on - DAC '11, 2011
    Co-Authors: Yi Wang, Zili Shao, Yong Guan
    Abstract:

    The new write constraints of multi-level cell (MLC) NAND Flash memory make most of the existing Flash Translation Layer (FTL) schemes inefficient or inapplicable. In this paper, we solve several fundamental problems in the design of MLC Flash Translation Layer. The objective is to reduce the garbage collection overhead so as to reduce the average system response time. We make the key observation that the valid page copy is the essential garbage collection overhead. Based on this observation, we propose two approaches, namely, concentrated mapping and postponed reclamation, to effective reduce the valid page copies. We conduct experiments on a set of benchmarks from both the real world and synthetic traces. The experimental results show that our scheme can achieve a significant reduction in the average system response time compared with the previous work.

Li-pin Chang - One of the best experts on this subject based on the ideXlab platform.

  • KVSSD: Close integration of LSM trees and Flash Translation Layer for write-efficient KV store
    2018 Design Automation & Test in Europe Conference & Exhibition (DATE), 2018
    Co-Authors: Sung-ming Wu, Li-pin Chang
    Abstract:

    Log-Structured-Merge (LSM) trees are a write-optimized data structure for lightweight, high-performance Key-Value (KV) store. Solid State Disks (SSDs) provide acceleration of KV operations on LSM trees. However, this hierarchical design involves multiple software Layers, including the LSM tree, host file system, and Flash Translation Layer (FTL), causing cascading write amplifications. We propose KVSSD, a close integration of LSM trees and the FTL, to manage write amplifications from different Layers. KVSSD exploits the FTL mapping mechanism to implement copy-free compaction of LSM trees, and it enables direct data allocation in Flash memory for efficient garbage collection. In our experiments, compared to the hierarchical design, our KVSSD reduced the write amplification by 88% and improved the throughput by 347%.

  • DATE - KVSSD: Close integration of LSM trees and Flash Translation Layer for write-efficient KV store
    2018 Design Automation & Test in Europe Conference & Exhibition (DATE), 2018
    Co-Authors: Sung-ming Wu, Li-pin Chang
    Abstract:

    Log-Structured-Merge (LSM) trees are a write-optimized data structure for lightweight, high-performance Key-Value (KV) store. Solid State Disks (SSDs) provide acceleration of KV operations on LSM trees. However, this hierarchical design involves multiple software Layers, including the LSM tree, host file system, and Flash Translation Layer (FTL), causing cascading write amplifications. We propose KVSSD, a close integration of LSM trees and the FTL, to manage write amplifications from different Layers. KVSSD exploits the FTL mapping mechanism to implement copy-free compaction of LSM trees, and it enables direct data allocation in Flash memory for efficient garbage collection. In our experiments, compared to the hierarchical design, our KVSSD reduced the write amplification by 88% and improved the throughput by 347%.

  • Integrating LSM Trees with Multichip Flash Translation Layer for Write-Efficient KVSSDs
    IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1
    Co-Authors: Sung-ming Wu, Li-pin Chang
    Abstract:

    Log-structured-merge (LSM) trees are a highly write-optimized data structure for lightweight, high-performance Key-Value (KV) stores. Furthermore, solid state drives (SSDs) are a crucial component for I/O acceleration. Conventional LSM-over-SSD designs involve multiple software Layers, including the LSM tree, host file system, and Flash Translation Layer (FTL), which introduce cascading write amplifications. To manage the write amplifications from different Layers, we propose KVSSDs, which are a close integration of LSM trees and the FTL. KVSSDs exploit the FTL mapping mechanism to implement copy-free compaction of LSM trees, and they enables direct data allocation in Flash memory for efficient garbage collection. Our design also uses a fine-grained, dynamic striping policy to fully exploit the rich internal parallelism of multichip SSDs. The experimental results indicated that our LSM-SSD integrated design reduced the write amplification by 86% and improved the throughput by 383% compared with a conventional LSM-over-SSD design.