The Experts below are selected from a list of 69 Experts worldwide ranked by ideXlab platform

Paul K. Muller - One of the best experts on this subject based on the ideXlab platform.

  • Understanding Soft Error Resiliency of Blue Gene/Q Compute Chip through Hardware Proton Irradiation and Software Fault Injection
    SC '14: Proceedings of the International Conference for High Performance Computing Networking Storage and Analysis, 2014
    Co-Authors: Chen-yong Cher, Meeta S. Gupta, Pradip Bose, Paul K. Muller
    Abstract:

    Soft Error Resiliency is a major concern for Petascale high performance computing (HPC) systems. Blue Gene/Q (BG/Q) is the third generation of IBM's massively parallel, energy efficient Blue Gene series of supercomputers. The principal goal of this work is to understand the interaction between Blue-Gene/Q's hardware resiliency features and high-performance applications through proton irradiation of a real chip, and software resiliency inherent in these applications through application-level fault injection (AFI) experiments. From the proton irradiation experiments we derived that the mean time between correctable errors at sea level of the SRAM-based Register files and Level-1 caches for a system similar to the scale of Sequoia system. From the AFI experiments, we characterized relative vulnerability among the applications in both general purpose and floating point Register files. We categorized and quantified the failure outcomes, and discovered characteristics in the applications that lead to many masking improvement opportunities.

Shekhar Borkar - One of the best experts on this subject based on the ideXlab platform.

  • VLSIC - A 2.8GHz 128-entry × 152b 3-read/2-write multi-precision Floating-Point Register file and shuffler in 32nm CMOS
    2012 Symposium on VLSI Circuits (VLSIC), 2012
    Co-Authors: Steven K. Hsu, Amit Agarwal, Mark A. Anders, Himanshu Kaul, Sanu K. Mathew, Farhana Sheikh, Ram Krishnamurthy, Shekhar Borkar
    Abstract:

    A 128-entry × 152b 3-read/2-write ported multi-precision Floating-Point Register file/shuffler with measured 2.8GHz operation is fabricated in 1.05V, 32nm CMOS. Single-precision (24b-mantissa), 2-way 12b or 4-way 6b reduced mantissa precision modes, certainty tracking bits, mode-dependent gating, area-efficient windowing using 1R/1W cells, and ultra-low-voltage read/write circuits enable 350mV–1.2V wide dynamic voltage range with measured peak energy-efficiency of 751GOPS/W at 400mV, 4-way 6b-mode (22.3× higher than 1.05V single-precision mode) and 19% area reduction over single-precision 3R/2W implementations.

Chen-yong Cher - One of the best experts on this subject based on the ideXlab platform.

  • Understanding Soft Error Resiliency of Blue Gene/Q Compute Chip through Hardware Proton Irradiation and Software Fault Injection
    SC '14: Proceedings of the International Conference for High Performance Computing Networking Storage and Analysis, 2014
    Co-Authors: Chen-yong Cher, Meeta S. Gupta, Pradip Bose, Paul K. Muller
    Abstract:

    Soft Error Resiliency is a major concern for Petascale high performance computing (HPC) systems. Blue Gene/Q (BG/Q) is the third generation of IBM's massively parallel, energy efficient Blue Gene series of supercomputers. The principal goal of this work is to understand the interaction between Blue-Gene/Q's hardware resiliency features and high-performance applications through proton irradiation of a real chip, and software resiliency inherent in these applications through application-level fault injection (AFI) experiments. From the proton irradiation experiments we derived that the mean time between correctable errors at sea level of the SRAM-based Register files and Level-1 caches for a system similar to the scale of Sequoia system. From the AFI experiments, we characterized relative vulnerability among the applications in both general purpose and floating point Register files. We categorized and quantified the failure outcomes, and discovered characteristics in the applications that lead to many masking improvement opportunities.

K. Safford - One of the best experts on this subject based on the ideXlab platform.

  • The Parity protected, multithreaded Register files on the 90-nm itanium microprocessor
    IEEE Journal of Solid-State Circuits, 2006
    Co-Authors: E.s. Fetzer, D. Dahle, C. Little, K. Safford
    Abstract:

    The integer and Floating-Point Register files of the 90-nm generation Itanium Microprocessor are described. A pulsed, shared word line technique enables a 22 ported integer array with only 12 word lines per Register. An in-Register ripple parity system provides soft error detection with no impact to operand bypass or pipeline depth while keeping consuming less that 6% of the total Register datapath area. The Register file implements temporal multi-threading by multiplexing the read and write ports to two storage nodes enabling Registers to write both foreground and background threads to the same Register at the same time. Thread switching completes in one cycle. The Register files are fabricated in a 7-layer 90-nm process and operate up to 2.0 GHz while consuming 400 mW per Register array.

José F. Martínez - One of the best experts on this subject based on the ideXlab platform.

  • DepCoS-RELCOMEX - XML Schema Based Faultset Definition to Improve Faults Injection Tools Interoperability
    2008 Third International Conference on Dependability of Computer Systems DepCoS-RELCOMEX, 2008
    Co-Authors: Antonio Da Silva, José F. Martínez, Lourdes López, Ana Belén García, Vicente Hernández
    Abstract:

    This paper describes an XML schema formalization approach for the definition of basic fault sets which specify memory and/or Register value corruption in microprocessor-based systems. SWIFI (software implemented fault injection) tools use fault injectors to carry out the fault injection campaign defined in a GUI-based application. However, the communication between the fault injector and the application is defined in an ad-hoc manner. Through this proposed XML schema definition different injectors could be used to carry out the same fault set injection. To validate this approach floating point Register and memory corruptions with temporal triggers and routine interception mechanisms to carry out argument and return value, corruption has been considered. Moreover, an experimental tool called Exhaustifreg, consisting of a GUI Java application for defining the fault sets and injection policies and two injectors for SPARC and i386 architectures under RTEMS, has been developed. The XML-based approach improves the interoperability between SWIFI tools by uncoupling the injectors from the experiment manager in charge of the fault campaign.

  • EATIS - Exhaustif®: a fault injection tool for distributed heterogeneous embedded systems
    Proceedings of the 2007 Euro American conference on Telematics and information systems - EATIS '07, 2007
    Co-Authors: Antonio Dasilva, José F. Martínez, Lourdes López, Ana Belén García, L.m. Redondo
    Abstract:

    This paper presents Exhaustif®, a SWIFI fault injection tool for fault tolerance verification and the validation of embedded software in distributed heterogeneous systems. Exhaustif® mainly consists of two parts: EEM and FIK. Exhaustif® Executive Manager (EEM) is a GUI Java application to define the fault injection campaign that uses a SQL database to save the test results obtained from the System under Test (SUT) in order to carry out a post injection data analysis. FIK is under the command of EEM to cary out fault injections in applications running under diverse operating systems using pure SWIFI techniques. Exhaustif® carries out floating point Register and memory corruptions using temporary triggers and uses an optimized routine interception mechanism to carry out argument and return value corruption with a minimal time overhead. Two experimental Fault Injector Kernels (FIK) under the RTEMS operating system for an EADS-Astrium SPARC ERC32-based MCM processor board and i386 standard PC mainboard have been developed.