The Experts below are selected from a list of 648 Experts worldwide ranked by ideXlab platform

Esther Rodriguez-villegas - One of the best experts on this subject based on the ideXlab platform.

  • An inverse filter realisation of a single scale Inverse continuous wavelet Transform
    2008 IEEE International Symposium on Circuits and Systems, 2008
    Co-Authors: Alexander J. Casson, Esther Rodriguez-villegas
    Abstract:

    This work considers continuous time filter design for the inverse continuous wavelet Transform (ICWT) allowing the ICWT to be carried out for an arbitrary bandpass filter Forward Transform. The design procedure illustrates how application specific information can be used to guide the design process, for example to achieve good reconstruction from coefficients at just one analysis scale. Simulations of the filter design show that good reconstruction accuracy can be achieved.

  • ISCAS - An inverse filter realisation of a single scale Inverse continuous wavelet Transform
    2008 IEEE International Symposium on Circuits and Systems, 2008
    Co-Authors: Alexander J. Casson, Esther Rodriguez-villegas
    Abstract:

    This work considers continuous time filter design for the inverse continuous wavelet Transform (ICWT) allowing the ICWT to be carried out for an arbitrary bandpass filter Forward Transform. The design procedure illustrates how application specific information can be used to guide the design process, for example to achieve good reconstruction from coefficients at just one analysis scale. Simulations of the filter design show that good reconstruction accuracy can be achieved.

Ilker Hamzaoglu - One of the best experts on this subject based on the ideXlab platform.

  • EUSIPCO - A high performance and low cost hardware architecture for H.264 Transform and quantization algorithms
    2005
    Co-Authors: Ozgur Tasdizen, Ilker Hamzaoglu
    Abstract:

    In this paper, we present a high performance and low cost hardware architecture for real-time implementation of Forward Transform and quantization and inverse Transform and quantization algorithms used in H.264 / MPEG4 Part 10 video coding standard. The hardware architecture is based on a reconfigurable datapath with only one multiplier. This hardware is designed to be used as part of a complete low power H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 81 MHz in a Xilinx Virtex II FPGA and it is verified to work at 210 MHz in a 0.18µ ASIC implementation. The FPGA and ASIC implementations can code 27 and 70 VGA frames (640×480) per second respectively.

  • A high performance and low cost hardware architecture for H.264 Transform and quantization algorithms
    2005 13th European Signal Processing Conference, 2005
    Co-Authors: Ozgur Tasdizen, Ilker Hamzaoglu
    Abstract:

    In this paper, we present a high performance and low cost hardware architecture for real-time implementation of Forward Transform and quantization and inverse Transform and quantization algorithms used in H.264 / MPEG4 Part 10 video coding standard. The hardware architecture is based on a reconfigurable datapath with only one multiplier. This hardware is designed to be used as part of a complete low power H.264 video coding system for portable applications. The proposed architecture is implemented in Verilog HDL. The Verilog RTL code is verified to work at 81 MHz in a Xilinx Virtex II FPGA and it is verified to work at 210 MHz in a 0.18μ ASIC implementation. The FPGA and ASIC implementations can code 27 and 70 VGA frames (640×480) per second respectively.

Alexander J. Casson - One of the best experts on this subject based on the ideXlab platform.

  • An inverse filter realisation of a single scale Inverse continuous wavelet Transform
    2008 IEEE International Symposium on Circuits and Systems, 2008
    Co-Authors: Alexander J. Casson, Esther Rodriguez-villegas
    Abstract:

    This work considers continuous time filter design for the inverse continuous wavelet Transform (ICWT) allowing the ICWT to be carried out for an arbitrary bandpass filter Forward Transform. The design procedure illustrates how application specific information can be used to guide the design process, for example to achieve good reconstruction from coefficients at just one analysis scale. Simulations of the filter design show that good reconstruction accuracy can be achieved.

  • ISCAS - An inverse filter realisation of a single scale Inverse continuous wavelet Transform
    2008 IEEE International Symposium on Circuits and Systems, 2008
    Co-Authors: Alexander J. Casson, Esther Rodriguez-villegas
    Abstract:

    This work considers continuous time filter design for the inverse continuous wavelet Transform (ICWT) allowing the ICWT to be carried out for an arbitrary bandpass filter Forward Transform. The design procedure illustrates how application specific information can be used to guide the design process, for example to achieve good reconstruction from coefficients at just one analysis scale. Simulations of the filter design show that good reconstruction accuracy can be achieved.

Ivan V. Bajic - One of the best experts on this subject based on the ideXlab platform.

  • ISM - Robust Domain-Filling Plumb-Line Lens Distortion Correction
    2016 IEEE International Symposium on Multimedia (ISM), 2016
    Co-Authors: Mehdi P. Stapleton, Ivan V. Bajic
    Abstract:

    A new robust plumb-line lens distortion correction algorithm is proposed, which uses a Forward-Transform model. The proposed method offers three principal advantages over conventional methods. First, our approach requires fewer training samples to estimate correction parameters, which is an important practical advantage for cameras that are already installed and in use. Second, our method shows a greater degree of resistance to image noise. Finally, once the correction parameters are estimated, the corrected image completely fills the image domain and does not require any post processing, which allows for lower run-time complexity compared to conventional plumb-line methods.

  • Robust Domain-Filling Plumb-Line Lens Distortion Correction
    2016 IEEE International Symposium on Multimedia (ISM), 2016
    Co-Authors: Mehdi P. Stapleton, Ivan V. Bajic
    Abstract:

    A new robust plumb-line lens distortion correction algorithm is proposed, which uses a Forward-Transform model. The proposed method offers three principal advantages over conventional methods. First, our approach requires fewer training samples to estimate correction parameters, which is an important practical advantage for cameras that are already installed and in use. Second, our method shows a greater degree of resistance to image noise. Finally, once the correction parameters are estimated, the corrected image completely fills the image domain and does not require any post processing, which allows for lower run-time complexity compared to conventional plumb-line methods.

Chia-wei Chang - One of the best experts on this subject based on the ideXlab platform.

  • APCCAS - High-efficiency and cost-sharing architecture design of fast algorithm based multiple 4×4 and 8×8 Forward Transforms for multi-standard video encoder
    2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2016
    Co-Authors: Chia-wei Chang
    Abstract:

    In this work, fast algorithm-based multiple Transforms with a hardware-sharing design are exploited for 4×4 and 8×8 Forward Transforms in H.264/AVC, VC-1, HEVC, and AVS standards, and for 8×8 Forward Transforms in MPEG-1/2/4 schemes. The 4×4 VP8 and AVS-M fast Forward Transforms are developed by cost-sharing hardware for multi-standard video encoding applications. By matrix factorizations, our proposed 1D hardware-sharing Transform architecture is realized by only shifters and adders. Compared with the directly combined fast algorithms without hardware-sharing functionality, our proposed architecture reduces the number of shifters and adders by 24.5% and 73.4%, respectively. Compared with existing multi-standard Transform designs, our proposed architecture reveals larger normalized hardware efficiency. Our proposed hardware sharing based 1-D Forward Transform supports the Full HD (1920×1080@60Hz) specification with the 110.8MHz working frequency.

  • High-efficiency and cost-sharing architecture design of fast algorithm based multiple 4×4 and 8×8 Forward Transforms for multi-standard video encoder
    2016 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2016
    Co-Authors: Chia-wei Chang
    Abstract:

    In this work, fast algorithm-based multiple Transforms with a hardware-sharing design are exploited for 4×4 and 8×8 Forward Transforms in H.264/AVC, VC-1, HEVC, and AVS standards, and for 8×8 Forward Transforms in MPEG-1/2/4 schemes. The 4×4 VP8 and AVS-M fast Forward Transforms are developed by cost-sharing hardware for multi-standard video encoding applications. By matrix factorizations, our proposed 1D hardware-sharing Transform architecture is realized by only shifters and adders. Compared with the directly combined fast algorithms without hardware-sharing functionality, our proposed architecture reduces the number of shifters and adders by 24.5% and 73.4%, respectively. Compared with existing multi-standard Transform designs, our proposed architecture reveals larger normalized hardware efficiency. Our proposed hardware sharing based 1-D Forward Transform supports the Full HD (1920×1080@60Hz) specification with the 110.8MHz working frequency.

  • Efficient fast Transform processor with cost-effective hardware sharing architecture for multi-standard video encoding
    2012 5th International Congress on Image and Signal Processing, 2012
    Co-Authors: Chia-wei Chang
    Abstract:

    In this paper, fast multiple Forward Transform algorithms and their hardware sharing designs for 2x2, 4x4, and 8x8 Forward Transforms in H.264/AVC, and the 8x8 Forward Transform in AVS, 4x4 and 8x8 Forward Transforms in VC-1, and DCT in JPEG, MPEG-1/2/4 are developed with a cost effective hardware for the multi-standard video encoding applications. By only shift-and-addition computations, the proposed 1-D hardware sharing Transform scheme requires 16.5K gates and is achieved without multiplications. The proposed 1-D sharing architecture reduces the numbers of shifters and adders by up to 36% and 49% respectively, compared with the individual and separate fast algorithm schemes. By VLSI implementations, the 2-D Transform processor with the proposed 1-D sharing architecture achieves multi-standard real-time 1080HD video encoding.