The Experts below are selected from a list of 45 Experts worldwide ranked by ideXlab platform
Shoji Kawahito - One of the best experts on this subject based on the ideXlab platform.
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A high-speed, high-sensitivity digital CMOS image sensor with a global shutter and 12-bit column-parallel cyclic A/D converters
IEEE Journal of Solid-State Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integRated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the Full Frame Rate in excess of 3500 Frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal Full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mVrms, and the resulting signal dynamic range is 60 dB
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a high speed high sensitivity digital cmos image sensor with a global shutter and 12 bit column parallel cyclic a d converters
Symposium on VLSI Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512x512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integRated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-μm CMOS image sensor technology achieves the Full Frame Rate in excess of 3500 Frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lx ·s. The signal Full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8 mV rms , and the resulting signal dynamic range is 60 dB.
Masanori Furuta - One of the best experts on this subject based on the ideXlab platform.
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A high-speed, high-sensitivity digital CMOS image sensor with a global shutter and 12-bit column-parallel cyclic A/D converters
IEEE Journal of Solid-State Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integRated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the Full Frame Rate in excess of 3500 Frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal Full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mVrms, and the resulting signal dynamic range is 60 dB
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a high speed high sensitivity digital cmos image sensor with a global shutter and 12 bit column parallel cyclic a d converters
Symposium on VLSI Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512x512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integRated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-μm CMOS image sensor technology achieves the Full Frame Rate in excess of 3500 Frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lx ·s. The signal Full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8 mV rms , and the resulting signal dynamic range is 60 dB.
Yukinari Nishikawa - One of the best experts on this subject based on the ideXlab platform.
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A high-speed, high-sensitivity digital CMOS image sensor with a global shutter and 12-bit column-parallel cyclic A/D converters
IEEE Journal of Solid-State Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integRated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the Full Frame Rate in excess of 3500 Frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal Full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mVrms, and the resulting signal dynamic range is 60 dB
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a high speed high sensitivity digital cmos image sensor with a global shutter and 12 bit column parallel cyclic a d converters
Symposium on VLSI Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512x512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integRated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-μm CMOS image sensor technology achieves the Full Frame Rate in excess of 3500 Frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lx ·s. The signal Full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8 mV rms , and the resulting signal dynamic range is 60 dB.
Toru Inoue - One of the best experts on this subject based on the ideXlab platform.
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A high-speed, high-sensitivity digital CMOS image sensor with a global shutter and 12-bit column-parallel cyclic A/D converters
IEEE Journal of Solid-State Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512times512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integRated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-mum CMOS image sensor technology achieves the Full Frame Rate in excess of 3500 Frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lxmiddots. The signal Full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8mVrms, and the resulting signal dynamic range is 60 dB
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a high speed high sensitivity digital cmos image sensor with a global shutter and 12 bit column parallel cyclic a d converters
Symposium on VLSI Circuits, 2007Co-Authors: Masanori Furuta, Yukinari Nishikawa, Toru Inoue, Shoji KawahitoAbstract:This paper presents a high-speed, high-sensitivity 512x512 CMOS image sensor with column parallel cyclic 12-bit ADCs and a global electronic shutter. Each pixel has a charge amplifier for high charge-to-voltage conversion gain despite of using a large-size photodiode, and two sample-and-hold stages for the global shutter and fixed pattern noise (FPN) canceling. High-speed column-parallel cyclic ADC arrays with 12-bit resolution having a small layout size of 0.09 mm 2 are integRated at both sides of image array. A technique for accelerating the conversion speed using variable clocking and sampling capacitance is developed. A digital gain control function using 14-bit temporal digital code is also set in the column parallel ADC. The fabricated chip in 0.25-μm CMOS image sensor technology achieves the Full Frame Rate in excess of 3500 Frames/s. The in-pixel charge amplifier achieves the optical sensitivity of 19.9 V/lx ·s. The signal Full scale at the pixel output is 1.8 V at 3.3-V supply and the noise level is measured to be 1.8 mV rms , and the resulting signal dynamic range is 60 dB.
Luca Berdondini - One of the best experts on this subject based on the ideXlab platform.
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large scale high resolution data acquisition system for extracellular recording of electrophysiological activity
IEEE Transactions on Biomedical Engineering, 2008Co-Authors: K Imfeld, S Neukom, Alessandro Maccione, Y Bornat, Sergio Martinoia, Pierreandre Farine, M Koudelkahep, Luca BerdondiniAbstract:A platform for high spatial and temporal resolution electrophysiological recordings of in vitro electrogenic cell cultures handling 4096 electrodes at a Full Frame Rate of 8 kHz is presented and validated by means of cardiomyocyte cultures. Based on an active pixel sensor device implementing an array of metallic electrodes, the system provides acquisitions at spatial resolutions of 42 mum on an active area of 2.67 mm times 2.67 mm, and in the zooming mode, temporal resolutions down to 8 mus on 64 randomly selected electrodes. The low-noise performances of the integRated amplifier (11 muVrms) combined with a hardware implementation inspired by image/video processing concepts enable high-resolution acquisitions with real-time preprocessing capabilities adapted to the handling of the large amount of acquired data.
