The Experts below are selected from a list of 42102 Experts worldwide ranked by ideXlab platform
A.a. Jerraya - One of the best experts on this subject based on the ideXlab platform.
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A Generic Architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip
Annales Des Télécommunications, 2004Co-Authors: N. Zergainoh, Amer Baghdadi, A.a. JerrayaAbstract:In this paper, we describe a methodology and flow for systematic design of application specific multiprocessor system-on-chip (mp-SoC). Our approach is based on a Generic Architecture platform which is used as a model throughout the design process. This model is modular, flexible and scalable, making it possible to cover a large application field. A complete design flow from system specification to register transfer level (rtl) consists of two principal stages. The first stage is Architecture exploration where the system-level performance estimation method is required to find the best system Architecture. The goal of this stage is to fix the optimal architectural parameters specific to the application. The second stage is the systematic design flow. The architectural parameters are used in this stage to produce thertl Architecture. This paper focuses on the definition of the Architecture model and the systematic design flow that was now automated. The feasibility and effectiveness of this approach are illustrated by several telecommunication applications.
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A Generic Architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip
Annales Des Télécommunications, 2004Co-Authors: N. Zergainoh, Amer Baghdadi, A.a. JerrayaAbstract:Cet article propose une nouvelle approche de conception systématique d’Architectures multiprocesseurs monopuces ( mp -SoC) à application spécifique. Cette approache est basée sur une plateforme architecturale générique utilisée comme modèle de référence durant tout le cycle de conception. Ce modèle est modulaire, flexible et extensible, permettant de couvrir un large domaine d’applications. Un flot de conception complet est constitué de deux étapes principales : l’étape d’exploration des Architectures et l’étape de conception de l’Architecture. Le but de la première étape est de fixer les paramètres architecturaux (optimaux) spécifiques de l’application. Ces paramètres sont utilisés dans la seconde étape pour produire l’Architecture rtl . La deuxième étape adopte une approche systématique basée sur l’instanciation et la configuration de composants à partir de bibliothèques. Elle comporte trois types d’actions : la conception des composants logiciels (application et système), la conception des composants matériels et la conception du réseau de communication permettant d’intégrer les composants de base. Dans cet article, nous nous focalisons sur l’étude de la plateforme générique mp -SoC et sur le flot de conception systématique. Plusieurs applications industrielles aux télécommunications ont été réalisées pour évaluer et valider l’efficacité de cette approche. In this paper, we describe a methodology and flow for systematic design of application specific multiprocessor system-on-chip ( mp -SoC). Our approach is based on a Generic Architecture platform which is used as a model throughout the design process. This model is modular, flexible and scalable, making it possible to cover a large application field. A complete design flow from system specification to register transfer level ( rtl ) consists of two principal stages. The first stage is Architecture exploration where the system-level performance estimation method is required to find the best system Architecture. The goal of this stage is to fix the optimal architectural parameters specific to the application. The second stage is the systematic design flow. The architectural parameters are used in this stage to produce the rtl Architecture. This paper focuses on the definition of the Architecture model and the systematic design flow that was now automated. The feasibility and effectiveness of this approach are illustrated by several telecommunication applications.
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Generic Architecture platform for multiprocessor system-on-chip design
2000Co-Authors: Amer Baghdadi, N. Zergainoh, D. Lyonnard, A.a. JerrayaAbstract:We present a Generic Architecture model for multiprocessor embedded system-on-chip design. The proposed model is modular, flexible and scalable. It permits an efficient generation of multiprocessor Architectures for embedded systems on chip. This work forms a promised step towards the definition of an efficient multiprocessor SoC design environment applicable to a large application domain. The key point when defining such an environment is to define the Architecture model that will fix the class of Architectures handled by the system. The model allows for automatic Architecture generation. The chapter focuses on the definition of the Architecture model. The feasibility and effectiveness of this Architecture model is illustrated by a significant demonstration example
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DIPES - Generic Architecture Platform for Multiprocessor System-On-Chip Design
Architecture and Design of Distributed Embedded Systems, 2000Co-Authors: Amer Baghdadi, N. Zergainoh, D. Lyonnard, A.a. JerrayaAbstract:This chapter presents a Generic Architecture model for multiprocessor embedded system-on-chip design. The use of this model as a template in a system design environment allows for efficient generation of multiprocessor Architectures. The key characteristics of this model are its great modularity, flexibility and scalability which make it reusable for a large class of application. In addition, it allows for reusability of pre-designed blocks and automatic Architecture generation. This chapter focuses on the definition of the Architecture model. The feasibility and effectiveness of this Architecture model are illustrated by a significant demonstration example.
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Generic Architecture platform for multiprocessor embedded system-on-chip design
2000Co-Authors: Amer Baghdadi, N. Zergainoh, D. Lyonnard, A.a. JerrayaAbstract:In this paper, we present a Generic Architecture model for multiprocessor embedded system-on-chip design. The use of this model as a template in a system design environment allows for efficient generation of multiprocessor Architectures. The key characteristics of this model are its great modularity, flexibility and scalability which make it reusable for a large class of application. In addition, it allows for reusability of pre-designed blocks and automatic Architecture generation. This paper focuses on the definition of the Architecture model. The feasibility and effectiveness of this Architecture model are illustrated by a significant demonstration example.
N. Zergainoh - One of the best experts on this subject based on the ideXlab platform.
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A Generic Architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip
Annales Des Télécommunications, 2004Co-Authors: N. Zergainoh, Amer Baghdadi, A.a. JerrayaAbstract:In this paper, we describe a methodology and flow for systematic design of application specific multiprocessor system-on-chip (mp-SoC). Our approach is based on a Generic Architecture platform which is used as a model throughout the design process. This model is modular, flexible and scalable, making it possible to cover a large application field. A complete design flow from system specification to register transfer level (rtl) consists of two principal stages. The first stage is Architecture exploration where the system-level performance estimation method is required to find the best system Architecture. The goal of this stage is to fix the optimal architectural parameters specific to the application. The second stage is the systematic design flow. The architectural parameters are used in this stage to produce thertl Architecture. This paper focuses on the definition of the Architecture model and the systematic design flow that was now automated. The feasibility and effectiveness of this approach are illustrated by several telecommunication applications.
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A Generic Architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip
Annales Des Télécommunications, 2004Co-Authors: N. Zergainoh, Amer Baghdadi, A.a. JerrayaAbstract:Cet article propose une nouvelle approche de conception systématique d’Architectures multiprocesseurs monopuces ( mp -SoC) à application spécifique. Cette approache est basée sur une plateforme architecturale générique utilisée comme modèle de référence durant tout le cycle de conception. Ce modèle est modulaire, flexible et extensible, permettant de couvrir un large domaine d’applications. Un flot de conception complet est constitué de deux étapes principales : l’étape d’exploration des Architectures et l’étape de conception de l’Architecture. Le but de la première étape est de fixer les paramètres architecturaux (optimaux) spécifiques de l’application. Ces paramètres sont utilisés dans la seconde étape pour produire l’Architecture rtl . La deuxième étape adopte une approche systématique basée sur l’instanciation et la configuration de composants à partir de bibliothèques. Elle comporte trois types d’actions : la conception des composants logiciels (application et système), la conception des composants matériels et la conception du réseau de communication permettant d’intégrer les composants de base. Dans cet article, nous nous focalisons sur l’étude de la plateforme générique mp -SoC et sur le flot de conception systématique. Plusieurs applications industrielles aux télécommunications ont été réalisées pour évaluer et valider l’efficacité de cette approche. In this paper, we describe a methodology and flow for systematic design of application specific multiprocessor system-on-chip ( mp -SoC). Our approach is based on a Generic Architecture platform which is used as a model throughout the design process. This model is modular, flexible and scalable, making it possible to cover a large application field. A complete design flow from system specification to register transfer level ( rtl ) consists of two principal stages. The first stage is Architecture exploration where the system-level performance estimation method is required to find the best system Architecture. The goal of this stage is to fix the optimal architectural parameters specific to the application. The second stage is the systematic design flow. The architectural parameters are used in this stage to produce the rtl Architecture. This paper focuses on the definition of the Architecture model and the systematic design flow that was now automated. The feasibility and effectiveness of this approach are illustrated by several telecommunication applications.
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A Generic Architecture platform based-methodology for an efficient design of Hardware/Software application-specific multiprocessor System-On-Chip
Annals of Telecommunications - annales des télécommunications, 2004Co-Authors: N. Zergainoh, Amer Baghdadi, A. Jerraya A.Abstract:In this paper, we describe a methodology and flow for systematic design of application specific multiprocessor system-on-chip (MP-SoC). Our approach is based on a Generic Architecture platform which is used as a model throughout the design process. This model is modular, flexible and scalable, making it possible to cover a large application field. A complete design flow from system specification to register transfer level (RTL) is consists of two principal stages. The first stage is Architecture exploration where the system-level performance estimation method is required to find the best system Architecture. The goal of this stage is to fix the optimal architectural parameters specific to the application. The second stage is the systematic design flow. The architectural parameters are used in this stage to produce the RTL Architecture. This paper focuses on the definition of the Architecture model and the systematic design flow that was now automated. The feasibility and effectiveness of this approach are illustrated by several telecommunication applications.
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Generic Architecture platform for multiprocessor system-on-chip design
2000Co-Authors: Amer Baghdadi, N. Zergainoh, D. Lyonnard, A.a. JerrayaAbstract:We present a Generic Architecture model for multiprocessor embedded system-on-chip design. The proposed model is modular, flexible and scalable. It permits an efficient generation of multiprocessor Architectures for embedded systems on chip. This work forms a promised step towards the definition of an efficient multiprocessor SoC design environment applicable to a large application domain. The key point when defining such an environment is to define the Architecture model that will fix the class of Architectures handled by the system. The model allows for automatic Architecture generation. The chapter focuses on the definition of the Architecture model. The feasibility and effectiveness of this Architecture model is illustrated by a significant demonstration example
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DIPES - Generic Architecture Platform for Multiprocessor System-On-Chip Design
Architecture and Design of Distributed Embedded Systems, 2000Co-Authors: Amer Baghdadi, N. Zergainoh, D. Lyonnard, A.a. JerrayaAbstract:This chapter presents a Generic Architecture model for multiprocessor embedded system-on-chip design. The use of this model as a template in a system design environment allows for efficient generation of multiprocessor Architectures. The key characteristics of this model are its great modularity, flexibility and scalability which make it reusable for a large class of application. In addition, it allows for reusability of pre-designed blocks and automatic Architecture generation. This chapter focuses on the definition of the Architecture model. The feasibility and effectiveness of this Architecture model are illustrated by a significant demonstration example.
Amer Baghdadi - One of the best experts on this subject based on the ideXlab platform.
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A Generic Architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip
Annales Des Télécommunications, 2004Co-Authors: N. Zergainoh, Amer Baghdadi, A.a. JerrayaAbstract:In this paper, we describe a methodology and flow for systematic design of application specific multiprocessor system-on-chip (mp-SoC). Our approach is based on a Generic Architecture platform which is used as a model throughout the design process. This model is modular, flexible and scalable, making it possible to cover a large application field. A complete design flow from system specification to register transfer level (rtl) consists of two principal stages. The first stage is Architecture exploration where the system-level performance estimation method is required to find the best system Architecture. The goal of this stage is to fix the optimal architectural parameters specific to the application. The second stage is the systematic design flow. The architectural parameters are used in this stage to produce thertl Architecture. This paper focuses on the definition of the Architecture model and the systematic design flow that was now automated. The feasibility and effectiveness of this approach are illustrated by several telecommunication applications.
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A Generic Architecture model based-methodology for an efficient design of hardware/software application-specific multiprocessor System-on-Chip
Annales Des Télécommunications, 2004Co-Authors: N. Zergainoh, Amer Baghdadi, A.a. JerrayaAbstract:Cet article propose une nouvelle approche de conception systématique d’Architectures multiprocesseurs monopuces ( mp -SoC) à application spécifique. Cette approache est basée sur une plateforme architecturale générique utilisée comme modèle de référence durant tout le cycle de conception. Ce modèle est modulaire, flexible et extensible, permettant de couvrir un large domaine d’applications. Un flot de conception complet est constitué de deux étapes principales : l’étape d’exploration des Architectures et l’étape de conception de l’Architecture. Le but de la première étape est de fixer les paramètres architecturaux (optimaux) spécifiques de l’application. Ces paramètres sont utilisés dans la seconde étape pour produire l’Architecture rtl . La deuxième étape adopte une approche systématique basée sur l’instanciation et la configuration de composants à partir de bibliothèques. Elle comporte trois types d’actions : la conception des composants logiciels (application et système), la conception des composants matériels et la conception du réseau de communication permettant d’intégrer les composants de base. Dans cet article, nous nous focalisons sur l’étude de la plateforme générique mp -SoC et sur le flot de conception systématique. Plusieurs applications industrielles aux télécommunications ont été réalisées pour évaluer et valider l’efficacité de cette approche. In this paper, we describe a methodology and flow for systematic design of application specific multiprocessor system-on-chip ( mp -SoC). Our approach is based on a Generic Architecture platform which is used as a model throughout the design process. This model is modular, flexible and scalable, making it possible to cover a large application field. A complete design flow from system specification to register transfer level ( rtl ) consists of two principal stages. The first stage is Architecture exploration where the system-level performance estimation method is required to find the best system Architecture. The goal of this stage is to fix the optimal architectural parameters specific to the application. The second stage is the systematic design flow. The architectural parameters are used in this stage to produce the rtl Architecture. This paper focuses on the definition of the Architecture model and the systematic design flow that was now automated. The feasibility and effectiveness of this approach are illustrated by several telecommunication applications.
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A Generic Architecture platform based-methodology for an efficient design of Hardware/Software application-specific multiprocessor System-On-Chip
Annals of Telecommunications - annales des télécommunications, 2004Co-Authors: N. Zergainoh, Amer Baghdadi, A. Jerraya A.Abstract:In this paper, we describe a methodology and flow for systematic design of application specific multiprocessor system-on-chip (MP-SoC). Our approach is based on a Generic Architecture platform which is used as a model throughout the design process. This model is modular, flexible and scalable, making it possible to cover a large application field. A complete design flow from system specification to register transfer level (RTL) is consists of two principal stages. The first stage is Architecture exploration where the system-level performance estimation method is required to find the best system Architecture. The goal of this stage is to fix the optimal architectural parameters specific to the application. The second stage is the systematic design flow. The architectural parameters are used in this stage to produce the RTL Architecture. This paper focuses on the definition of the Architecture model and the systematic design flow that was now automated. The feasibility and effectiveness of this approach are illustrated by several telecommunication applications.
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Generic Architecture platform for multiprocessor system-on-chip design
2000Co-Authors: Amer Baghdadi, N. Zergainoh, D. Lyonnard, A.a. JerrayaAbstract:We present a Generic Architecture model for multiprocessor embedded system-on-chip design. The proposed model is modular, flexible and scalable. It permits an efficient generation of multiprocessor Architectures for embedded systems on chip. This work forms a promised step towards the definition of an efficient multiprocessor SoC design environment applicable to a large application domain. The key point when defining such an environment is to define the Architecture model that will fix the class of Architectures handled by the system. The model allows for automatic Architecture generation. The chapter focuses on the definition of the Architecture model. The feasibility and effectiveness of this Architecture model is illustrated by a significant demonstration example
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DIPES - Generic Architecture Platform for Multiprocessor System-On-Chip Design
Architecture and Design of Distributed Embedded Systems, 2000Co-Authors: Amer Baghdadi, N. Zergainoh, D. Lyonnard, A.a. JerrayaAbstract:This chapter presents a Generic Architecture model for multiprocessor embedded system-on-chip design. The use of this model as a template in a system design environment allows for efficient generation of multiprocessor Architectures. The key characteristics of this model are its great modularity, flexibility and scalability which make it reusable for a large class of application. In addition, it allows for reusability of pre-designed blocks and automatic Architecture generation. This chapter focuses on the definition of the Architecture model. The feasibility and effectiveness of this Architecture model are illustrated by a significant demonstration example.
Wouter Joosen - One of the best experts on this subject based on the ideXlab platform.
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a Generic Architecture for web applications to support threat analysis of infrastructural components
Communications and Multimedia Security, 2005Co-Authors: Lieven Desmet, Bart Jacobs, Frank Piessens, Wouter JoosenAbstract:In order to perform a useful threat analysis of a web application platform, some architectural assumptions about such applications must be made. This document describes a Generic Architecture for typical 3-tier web applications. It serves as the basis for analyzing the threats in the most important infrastructural components in that Architecture, presented in the following papers.
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Communications and Multimedia Security - A Generic Architecture for Web Applications to Support Threat Analysis of Infrastructural Components
IFIP — The International Federation for Information Processing, 2005Co-Authors: Lieven Desmet, Bart Jacobs, Frank Piessens, Wouter JoosenAbstract:In order to perform a useful threat analysis of a web application platform, some architectural assumptions about such applications must be made. This document describes a Generic Architecture for typical 3-tier web applications. It serves as the basis for analyzing the threats in the most important infrastructural components in that Architecture, presented in the following papers.
Lieven Desmet - One of the best experts on this subject based on the ideXlab platform.
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a Generic Architecture for web applications to support threat analysis of infrastructural components
Communications and Multimedia Security, 2005Co-Authors: Lieven Desmet, Bart Jacobs, Frank Piessens, Wouter JoosenAbstract:In order to perform a useful threat analysis of a web application platform, some architectural assumptions about such applications must be made. This document describes a Generic Architecture for typical 3-tier web applications. It serves as the basis for analyzing the threats in the most important infrastructural components in that Architecture, presented in the following papers.
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Communications and Multimedia Security - A Generic Architecture for Web Applications to Support Threat Analysis of Infrastructural Components
IFIP — The International Federation for Information Processing, 2005Co-Authors: Lieven Desmet, Bart Jacobs, Frank Piessens, Wouter JoosenAbstract:In order to perform a useful threat analysis of a web application platform, some architectural assumptions about such applications must be made. This document describes a Generic Architecture for typical 3-tier web applications. It serves as the basis for analyzing the threats in the most important infrastructural components in that Architecture, presented in the following papers.