The Experts below are selected from a list of 303 Experts worldwide ranked by ideXlab platform
K Correll - One of the best experts on this subject based on the ideXlab platform.
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implementing neon a 256 bit Graphics Accelerator
IEEE Micro, 1999Co-Authors: Joel Mccormack, Larry D. Seiler, R Mcnamara, C Gianos, Norman P Jouppi, T Dutton, J Zurawski, K CorrellAbstract:High-performance 3D Graphics Accelerators traditionally require multiple chips on multiple boards. In contrast, Neon-a single chip-performs like a multichip design, accelerating openGL 3D rendering and X11 and windows/NT 2D rendering.
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neon a single chip 3d workstation Graphics Accelerator
International Conference on Computer Graphics and Interactive Techniques, 1998Co-Authors: Joel Mccormack, Larry D. Seiler, C Gianos, Norman P Jouppi, Robert S Mcnamara, K CorrellAbstract:High-performance 3D Graphics Accelerators traditionally require multiple chips on multiple boards, including geometry, rasterizing, pixel processing, and texture mapping chips. These designs are often scalable: they can increase performance by using more chips. Scalability has obvious costs: a minimal configuration needs several chips, and some configurations must replicate texture maps. A less obvious cost is the almost irresistible temptation to replicate chips to increase performance, rather than to design individual chips for higher performance in the first place. In contrast, Neon is a single chip that performs like a multichip design. Neon accelerates OpenGL [19] 3D rendering, as well as X11 [20] and Windows/NT 2D rendering. Since our pin budget limited peak memory bandwidth, we designed Neon from the memory system upward in order to reduce bandwidth requirements. Neon has no special-purpose memories; its eight independent 32-bit memory controllers can access color buffers, Z depth buffers, stencil buffers, and texture data. To fit our gate budget, we shared logic among different operations with similar implementation requirements, and left floating point calculations to Digital s Alpha CPUs. Neon s performance is between HP s Visualize fx4 and fx6, and is well above SGI' s MXE for most operations. Neon-based boards cost much less than these competitors, due to a small part count and use of commodity SDRAMs.
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Workshop on Graphics Hardware - Neon: a single-chip 3D workstation Graphics Accelerator
Proceedings of the ACM SIGGRAPH EUROGRAPHICS workshop on Graphics hardware - HWWS '98, 1998Co-Authors: Joel Mccormack, Larry D. Seiler, C Gianos, Norman P Jouppi, Robert S Mcnamara, K CorrellAbstract:High-performance 3D Graphics Accelerators traditionally require multiple chips on multiple boards, including geometry, rasterizing, pixel processing, and texture mapping chips. These designs are often scalable: they can increase performance by using more chips. Scalability has obvious costs: a minimal configuration needs several chips, and some configurations must replicate texture maps. A less obvious cost is the almost irresistible temptation to replicate chips to increase performance, rather than to design individual chips for higher performance in the first place. In contrast, Neon is a single chip that performs like a multichip design. Neon accelerates OpenGL [19] 3D rendering, as well as X11 [20] and Windows/NT 2D rendering. Since our pin budget limited peak memory bandwidth, we designed Neon from the memory system upward in order to reduce bandwidth requirements. Neon has no special-purpose memories; its eight independent 32-bit memory controllers can access color buffers, Z depth buffers, stencil buffers, and texture data. To fit our gate budget, we shared logic among different operations with similar implementation requirements, and left floating point calculations to Digital s Alpha CPUs. Neon s performance is between HP s Visualize fx4 and fx6, and is well above SGI' s MXE for most operations. Neon-based boards cost much less than these competitors, due to a small part count and use of commodity SDRAMs.
Joel Mccormack - One of the best experts on this subject based on the ideXlab platform.
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implementing neon a 256 bit Graphics Accelerator
IEEE Micro, 1999Co-Authors: Joel Mccormack, Larry D. Seiler, R Mcnamara, C Gianos, Norman P Jouppi, T Dutton, J Zurawski, K CorrellAbstract:High-performance 3D Graphics Accelerators traditionally require multiple chips on multiple boards. In contrast, Neon-a single chip-performs like a multichip design, accelerating openGL 3D rendering and X11 and windows/NT 2D rendering.
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neon a single chip 3d workstation Graphics Accelerator
International Conference on Computer Graphics and Interactive Techniques, 1998Co-Authors: Joel Mccormack, Larry D. Seiler, C Gianos, Norman P Jouppi, Robert S Mcnamara, K CorrellAbstract:High-performance 3D Graphics Accelerators traditionally require multiple chips on multiple boards, including geometry, rasterizing, pixel processing, and texture mapping chips. These designs are often scalable: they can increase performance by using more chips. Scalability has obvious costs: a minimal configuration needs several chips, and some configurations must replicate texture maps. A less obvious cost is the almost irresistible temptation to replicate chips to increase performance, rather than to design individual chips for higher performance in the first place. In contrast, Neon is a single chip that performs like a multichip design. Neon accelerates OpenGL [19] 3D rendering, as well as X11 [20] and Windows/NT 2D rendering. Since our pin budget limited peak memory bandwidth, we designed Neon from the memory system upward in order to reduce bandwidth requirements. Neon has no special-purpose memories; its eight independent 32-bit memory controllers can access color buffers, Z depth buffers, stencil buffers, and texture data. To fit our gate budget, we shared logic among different operations with similar implementation requirements, and left floating point calculations to Digital s Alpha CPUs. Neon s performance is between HP s Visualize fx4 and fx6, and is well above SGI' s MXE for most operations. Neon-based boards cost much less than these competitors, due to a small part count and use of commodity SDRAMs.
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Workshop on Graphics Hardware - Neon: a single-chip 3D workstation Graphics Accelerator
Proceedings of the ACM SIGGRAPH EUROGRAPHICS workshop on Graphics hardware - HWWS '98, 1998Co-Authors: Joel Mccormack, Larry D. Seiler, C Gianos, Norman P Jouppi, Robert S Mcnamara, K CorrellAbstract:High-performance 3D Graphics Accelerators traditionally require multiple chips on multiple boards, including geometry, rasterizing, pixel processing, and texture mapping chips. These designs are often scalable: they can increase performance by using more chips. Scalability has obvious costs: a minimal configuration needs several chips, and some configurations must replicate texture maps. A less obvious cost is the almost irresistible temptation to replicate chips to increase performance, rather than to design individual chips for higher performance in the first place. In contrast, Neon is a single chip that performs like a multichip design. Neon accelerates OpenGL [19] 3D rendering, as well as X11 [20] and Windows/NT 2D rendering. Since our pin budget limited peak memory bandwidth, we designed Neon from the memory system upward in order to reduce bandwidth requirements. Neon has no special-purpose memories; its eight independent 32-bit memory controllers can access color buffers, Z depth buffers, stencil buffers, and texture data. To fit our gate budget, we shared logic among different operations with similar implementation requirements, and left floating point calculations to Digital s Alpha CPUs. Neon s performance is between HP s Visualize fx4 and fx6, and is well above SGI' s MXE for most operations. Neon-based boards cost much less than these competitors, due to a small part count and use of commodity SDRAMs.
Hans-a. Bachor - One of the best experts on this subject based on the ideXlab platform.
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Four-dimensional multi-site two-photon excitation
Photonic Therapeutics and Diagnostics VI, 2010Co-Authors: Vincent Ricardo Daria, Christian Stricker, Richard Bowman, Hans-a. Bachor, Stephen J. RedmanAbstract:We use the holographic method to project an arbitrary array of diffraction-limited focal spots suitable for multi-site twophoton excitation. The spot array can be projected arbitrarily within a three-dimensional (3D) volume, while the fourth dimension in time is attributed to high temporal resolution via high-speed non-iterative calculation of the hologram using a video Graphics Accelerator board. We show that the spots have sufficient energy and spatiotemporal photon density for localized two-photon excitation at individual spots in the array. The significance of this work points to 3D microscopy, non-linear micro-fabrication, volume holographic optical storage and biomedical instrumentation. In neuroscience, timecritical release of neurotransmitters at multiple sites within complex dendritic trees of neurons can lead to insights on the mechanisms of information processing in the brain.
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Arbitrary multisite two-photon excitation in four dimensions
Applied Physics Letters, 2009Co-Authors: Vincent Ricardo Daria, Christian Stricker, Richard Bowman, Stephen J. Redman, Hans-a. BachorAbstract:We demonstrate dynamic and arbitrary multisite two-photon excitation in three dimensions using the holographic projection method. Rapid response (fourth dimension) is achieved through high-speed noniterative calculation of the hologram using a video Graphics Accelerator board. We verify that the projected asymmetric spot configurations have sufficient spatiotemporal photon density for localized two-photon excitation. This system is a significant advance and can be applied to time-resolved photolysis of caged compounds in biological cells and complex neuronal networks, nonlinear microfabrication and volume holographic optical storage.
Larry D. Seiler - One of the best experts on this subject based on the ideXlab platform.
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implementing neon a 256 bit Graphics Accelerator
IEEE Micro, 1999Co-Authors: Joel Mccormack, Larry D. Seiler, R Mcnamara, C Gianos, Norman P Jouppi, T Dutton, J Zurawski, K CorrellAbstract:High-performance 3D Graphics Accelerators traditionally require multiple chips on multiple boards. In contrast, Neon-a single chip-performs like a multichip design, accelerating openGL 3D rendering and X11 and windows/NT 2D rendering.
-
neon a single chip 3d workstation Graphics Accelerator
International Conference on Computer Graphics and Interactive Techniques, 1998Co-Authors: Joel Mccormack, Larry D. Seiler, C Gianos, Norman P Jouppi, Robert S Mcnamara, K CorrellAbstract:High-performance 3D Graphics Accelerators traditionally require multiple chips on multiple boards, including geometry, rasterizing, pixel processing, and texture mapping chips. These designs are often scalable: they can increase performance by using more chips. Scalability has obvious costs: a minimal configuration needs several chips, and some configurations must replicate texture maps. A less obvious cost is the almost irresistible temptation to replicate chips to increase performance, rather than to design individual chips for higher performance in the first place. In contrast, Neon is a single chip that performs like a multichip design. Neon accelerates OpenGL [19] 3D rendering, as well as X11 [20] and Windows/NT 2D rendering. Since our pin budget limited peak memory bandwidth, we designed Neon from the memory system upward in order to reduce bandwidth requirements. Neon has no special-purpose memories; its eight independent 32-bit memory controllers can access color buffers, Z depth buffers, stencil buffers, and texture data. To fit our gate budget, we shared logic among different operations with similar implementation requirements, and left floating point calculations to Digital s Alpha CPUs. Neon s performance is between HP s Visualize fx4 and fx6, and is well above SGI' s MXE for most operations. Neon-based boards cost much less than these competitors, due to a small part count and use of commodity SDRAMs.
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Workshop on Graphics Hardware - Neon: a single-chip 3D workstation Graphics Accelerator
Proceedings of the ACM SIGGRAPH EUROGRAPHICS workshop on Graphics hardware - HWWS '98, 1998Co-Authors: Joel Mccormack, Larry D. Seiler, C Gianos, Norman P Jouppi, Robert S Mcnamara, K CorrellAbstract:High-performance 3D Graphics Accelerators traditionally require multiple chips on multiple boards, including geometry, rasterizing, pixel processing, and texture mapping chips. These designs are often scalable: they can increase performance by using more chips. Scalability has obvious costs: a minimal configuration needs several chips, and some configurations must replicate texture maps. A less obvious cost is the almost irresistible temptation to replicate chips to increase performance, rather than to design individual chips for higher performance in the first place. In contrast, Neon is a single chip that performs like a multichip design. Neon accelerates OpenGL [19] 3D rendering, as well as X11 [20] and Windows/NT 2D rendering. Since our pin budget limited peak memory bandwidth, we designed Neon from the memory system upward in order to reduce bandwidth requirements. Neon has no special-purpose memories; its eight independent 32-bit memory controllers can access color buffers, Z depth buffers, stencil buffers, and texture data. To fit our gate budget, we shared logic among different operations with similar implementation requirements, and left floating point calculations to Digital s Alpha CPUs. Neon s performance is between HP s Visualize fx4 and fx6, and is well above SGI' s MXE for most operations. Neon-based boards cost much less than these competitors, due to a small part count and use of commodity SDRAMs.
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Integrating Video Rendering into Graphics Accelerator Chips
Digital Technical Journal, 1995Co-Authors: Larry D. Seiler, Robert A. UlichneyAbstract:The fusion of multimedia and traditional computer Graphics has long been predicted but has been slow to happen. The delay is due to many factors, including their dramatically different data type and bandwidth requirements. Digital has designed a pair of related Graphics Accelerator chips that integrate video rendering primitives with two-dimensional and threedimensional synthetic Graphics primitives. The chips perform one-dimensional filtering and scaling on either YUV or RGB source data. One implementation dithers YUV source data down to 256 colors. The other converts YUV to 24-bit RGB, which is then optionally dithered. Both chips leave image decompression to the CPU. The result is significantly faster frame rates at higher video quality, especially for displaying enlarged images. The paper compares the implementation cost of various design alternatives and presents performance comparisons with software image rendering.
Vincent Ricardo Daria - One of the best experts on this subject based on the ideXlab platform.
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Four-dimensional multi-site two-photon excitation
Photonic Therapeutics and Diagnostics VI, 2010Co-Authors: Vincent Ricardo Daria, Christian Stricker, Richard Bowman, Hans-a. Bachor, Stephen J. RedmanAbstract:We use the holographic method to project an arbitrary array of diffraction-limited focal spots suitable for multi-site twophoton excitation. The spot array can be projected arbitrarily within a three-dimensional (3D) volume, while the fourth dimension in time is attributed to high temporal resolution via high-speed non-iterative calculation of the hologram using a video Graphics Accelerator board. We show that the spots have sufficient energy and spatiotemporal photon density for localized two-photon excitation at individual spots in the array. The significance of this work points to 3D microscopy, non-linear micro-fabrication, volume holographic optical storage and biomedical instrumentation. In neuroscience, timecritical release of neurotransmitters at multiple sites within complex dendritic trees of neurons can lead to insights on the mechanisms of information processing in the brain.
-
Arbitrary multisite two-photon excitation in four dimensions
Applied Physics Letters, 2009Co-Authors: Vincent Ricardo Daria, Christian Stricker, Richard Bowman, Stephen J. Redman, Hans-a. BachorAbstract:We demonstrate dynamic and arbitrary multisite two-photon excitation in three dimensions using the holographic projection method. Rapid response (fourth dimension) is achieved through high-speed noniterative calculation of the hologram using a video Graphics Accelerator board. We verify that the projected asymmetric spot configurations have sufficient spatiotemporal photon density for localized two-photon excitation. This system is a significant advance and can be applied to time-resolved photolysis of caged compounds in biological cells and complex neuronal networks, nonlinear microfabrication and volume holographic optical storage.
