The Experts below are selected from a list of 41442 Experts worldwide ranked by ideXlab platform
Ju-ho Sohn - One of the best experts on this subject based on the ideXlab platform.
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A 195 mW, 9.1 MVertices/s Fully Programmable 3-D Graphics Processor for Low-Power Mobile Devices
IEEE Journal of Solid-State Circuits, 2008Co-Authors: Ju-ho SohnAbstract:A 195 mW, 9.1 Mvertices/s fully programmable 3-D Graphics Processor is designed and implemented for mobile devices. The mobile unified shader provides programmable per-vertex operations and per-pixel operations in a single hardware and thus, it achieves 35% area and 28% power reduction compared with previous architecture. The pixel-vertex multi-threading enhances the 3-D Graphics performance by enabling to compute the per-vertex operations and the per-pixel operations at the same time. By adopting the pixel-vertex multi-threading, 94% of the per-vertex operations are interleaved into the per-pixel operations and enhances 3-D Graphics performance in real applications. The logarithmic lighting engine and specialized lighting instruction improve the vertex throughput including transform and OpenGL lighting up to 9.1 Mvertices/s, which is 2.5 times higher performance compared with previous works. The proposed 3-D Graphics Processor is implemented in 3.3 mmtimes3.0 mm using 0.13 mum CMOS process and it was successfully demonstrated on the system evaluation board.
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a 195 mw 9 1 mvertices s fully programmable 3 d Graphics Processor for low power mobile devices
Asian Solid-State Circuits Conference, 2007Co-Authors: Ju-ho Sohn, Jongcheol Jeong, Euljoo JeongAbstract:A 195 mW, 9.1 Mvertices/s fully programmable 3-D Graphics Processor is designed and implemented for mobile devices. The mobile unified shader provides programmable per-vertex operations and per-pixel operations in a single hardware and thus, it achieves 35% area and 28% power reduction compared with previous architecture. The pixel-vertex multi-threading enhances the 3-D Graphics performance by enabling to compute the per-vertex operations and the per-pixel operations at the same time. By adopting the pixel-vertex multi-threading, 94% of the per-vertex operations are interleaved into the per-pixel operations and enhances 3-D Graphics performance in real applications. The logarithmic lighting engine and specialized lighting instruction improve the vertex throughput including transform and OpenGL lighting up to 9.1 Mvertices/s, which is 2.5 times higher performance compared with previous works. The proposed 3-D Graphics Processor is implemented in 3.3 mmtimes3.0 mm using 0.13 mum CMOS process and it was successfully demonstrated on the system evaluation board.
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A 195mW, 9.1MVertices/s fully programmable 3D Graphics Processor for low power mobile devices
2007 IEEE Asian Solid-State Circuits Conference, 2007Co-Authors: Ju-ho Sohn, Jongcheol Jeong, Euljoo JeongAbstract:A 195 mW, 9.1Mvertices/s fully programmable 3D Graphics engine is designed and implemented in 0.13 mum CMOS process for mobile devices. The power-optimized unified shader architecture provides high performance programmable vertex shading and programmable pixel shading with 35% area and 28% power reduction. The logarithmic lighting engine and specialized lighting instruction improves the vertex throughput to 9. 1Mvertices/s including full OpenGL lighting, which is 2.5 times higher performance compared with previous works. The 313 Graphics engine was successfully demonstrated on the system evaluation board.
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A 155-mW 50-m vertices/s Graphics Processor with fixed-point programmable vertex shader for mobile applications
IEEE Journal of Solid-State Circuits, 2006Co-Authors: Ju-ho SohnAbstract:A 36 mm/sup 2/ Graphics Processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) Graphics applications. The Graphics Processor contains an ARM-10 compatible 32-bit RISC Processor,a 128-bit programmable fixed-point single-instruction-multiple-data (SIMD)vertex shader, a low-power rendering engine, and a programmable frequency synthesizer (PFS). Different from conventional Graphics hardware, the proposed Graphics Processor implements ARM-10 co-Processor architecture with dual operations so that user-programmable vertex shading is possible for advanced Graphics algorithms and various streaming multimedia processing in mobile applications. The circuits and architecture of the Graphics Processor are optimized for fixed-point operations and achieve the low power consumption with help of instruction-level power management of the vertex shader and pixel-level clock gating of the rendering engine. The PFS with a fully balanced voltage-controlled oscillator (VCO) controls the clock frequency from 8 MHz to 271 MHz continuously and adaptively for low-power modes by software. The chip shows 50 Mvertices/s and 200 Mtexels/s peak Graphics performance, dissipating 155 mW in 0.18-/spl mu/m 6-metal standard CMOS logic process.
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a 155 mw 50 m vertices s Graphics Processor with fixed point programmable vertex shader for mobile applications
International Solid-State Circuits Conference, 2005Co-Authors: Ju-ho SohnAbstract:A 36 mm/sup 2/ Graphics Processor with fixed-point programmable vertex shader is designed and implemented for portable two-dimensional (2-D) and three-dimensional (3-D) Graphics applications. The Graphics Processor contains an ARM-10 compatible 32-bit RISC Processor,a 128-bit programmable fixed-point single-instruction-multiple-data (SIMD)vertex shader, a low-power rendering engine, and a programmable frequency synthesizer (PFS). Different from conventional Graphics hardware, the proposed Graphics Processor implements ARM-10 co-Processor architecture with dual operations so that user-programmable vertex shading is possible for advanced Graphics algorithms and various streaming multimedia processing in mobile applications. The circuits and architecture of the Graphics Processor are optimized for fixed-point operations and achieve the low power consumption with help of instruction-level power management of the vertex shader and pixel-level clock gating of the rendering engine. The PFS with a fully balanced voltage-controlled oscillator (VCO) controls the clock frequency from 8 MHz to 271 MHz continuously and adaptively for low-power modes by software. The chip shows 50 Mvertices/s and 200 Mtexels/s peak Graphics performance, dissipating 155 mW in 0.18-/spl mu/m 6-metal standard CMOS logic process.
Donald C. Wunsch - One of the best experts on this subject based on the ideXlab platform.
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ISIC - A Survey of Neural Computation on Graphics Processing Hardware
2007 IEEE 22nd International Symposium on Intelligent Control, 2007Co-Authors: Ryan J. Meuth, Donald C. WunschAbstract:Modern Graphics processing units (GPU) are used for much more than simply 3D Graphics applications. From machine vision to finite element analysis, CPU's are being used in diverse applications, collectively called general purpose Graphics Processor utilization. This paper explores the capabilities and limitations of modern GPU's and surveys the neural computation technologies that have been applied to these devices.
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A Survey of Neural Computation on Graphics Processing Hardware
2007 IEEE 22nd International Symposium on Intelligent Control, 2007Co-Authors: Ryan J. Meuth, Donald C. WunschAbstract:Modern Graphics processing units (GPU) are used for much more than simply 3D Graphics applications. From machine vision to finite element analysis, CPU's are being used in diverse applications, collectively called general purpose Graphics Processor utilization. This paper explores the capabilities and limitations of modern GPU's and surveys the neural computation technologies that have been applied to these devices.
Hoi-jun Yoo - One of the best experts on this subject based on the ideXlab platform.
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A 52.4mW 3D Graphics Processor with 141Mvertices/s vertex shader and 3 power domains of dynamic voltage and frequency scaling
Digest of Technical Papers - IEEE International Solid-State Circuits Conference, 2007Co-Authors: Byeong-Gyu Nam, Jeabin Lee, Kwanho Kim, Seung Jin Lee, Hoi-jun YooAbstract:A 3D Graphics Processor fabricated using 0.18mum 6M CMOS contains 1.57M transistors and 29kB SRAM in a core size of 17.2mm2. The vertex shader utilizes a logarithmic number system for 141 Mvertices/s and the 3 power domains are controlled separately by dynamic voltage and frequency scaling for 52.4mW at 60fps.
M.m. Okoniewski - One of the best experts on this subject based on the ideXlab platform.
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Acceleration of finite-difference time-domain (FDTD) using Graphics Processor units (GPU)
2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535), 2004Co-Authors: S.e. Krakiwsky, L.e. Turner, M.m. OkoniewskiAbstract:The Finite-Difference Time-Domain (FDTD) method is used extensively in areas of microwave engineering and optics. However, FDTD runs too slow for some simulations to be practical, especially when run on standard desktop computers. The suitability of dedicated hardware for the acceleration of FDTD computations has been investigated. It is demonstrated that standard consumer Graphics Processor Units (GPUs) can be used to accelerate FDTD simulations by a factor of over seven, relative to an Intel CPU of similar technology generation. With OpenGL as the Application Programming Interface (API), a standard commercial Graphics card has been programmed to solve a 2-D electromagnetic scattering problem.
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Graphics Processor unit (GPU) acceleration of finite-difference time-domain (FDTD) algorithm
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512), 2004Co-Authors: S.e. Krakiwsky, L.e. Turner, M.m. OkoniewskiAbstract:The finite-difference time-domain (FDTD) algorithm has become a tool of choice in many areas of RF and microwave engineering and optics. However, FDTD runs too slow for some simulations to be practical, even when carried out on supercomputers. The development of dedicated hardware to accelerate FDTD computations has been investigated. In this paper, we demonstrate that off-the-shelf Graphics Processor units (GPUs) can be successfully used to accelerate FDTD simulations. Using C++, OpenGL, and several OpenGL extensions, a modern GPU has been programmed to solve a simple two dimensional electromagnetic scattering problem. The GPU outperforms a central processing unit (CPU) of comparable technology generation.
Shigeru Sasaki - One of the best experts on this subject based on the ideXlab platform.
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3D Graphics Processor Chip Set
IEEE Micro, 1995Co-Authors: Makoto Awaga, Tatsushi Ohtsuka, Hideki Yoshizawa, Shigeru SasakiAbstract:Increasingly, 3D Graphics is becoming the rule rather than the exception in applications such as games, CAD/CAM and video production. A new chip set solves that problem using two Processors to render 300,000 polygons per second for performance comparable to that of advanced game machines.
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3D Graphics Processor chip set
IEEE Micro, 1995Co-Authors: Makoto Awaga, Tatsushi Ohtsuka, Hideki Yoshizawa, Shigeru SasakiAbstract:Increasingly, 3D Graphics is becoming the rule rather than the exception in applications such as games, CAD/CAM, and video production. Some LSIs provide rendering capabilities, but require an additional CPU to perform essential geometry transformations. Fujitsu's chip set solves that problem using two Processors to render 300,000 polygons per second (for flat-shaded triangles with texture)-performance comparable to that of advanced game machines.
