The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Woochan Park - One of the best experts on this subject based on the ideXlab platform.
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raycore a ray tracing Hardware Architecture for mobile devices
ACM Transactions on Graphics, 2014Co-Authors: Jaeho Nah, Hyuckjoo Kwon, Dongseok Kim, Cheolho Jeong, Jinhong Park, Tackdon Han, Dinesh Manocha, Woochan ParkAbstract:We present RayCore, a mobile ray-tracing Hardware Architecture. RayCore facilitates high-quality rendering effects, such as reflection, refraction, and shadows, on mobile devices by performing real-time Whitted ray tracing. RayCore consists of two major components: ray-tracing units (RTUs) based on a unified traversal and intersection pipeline and a tree-building unit (TBU) for dynamic scenes. The overall RayCore Architecture offers considerable benefits in terms of die area, memory access, and power consumption. We have evaluated our Architecture based on FPGA and ASIC evaluations and demonstrate its performance on different benchmarks. According to the results, our Architecture demonstrates high performance per unit area and unit energy, making it highly suitable for use in mobile devices.
John J. Wade - One of the best experts on this subject based on the ideXlab platform.
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SPANNER: A Self-Repairing Spiking Neural Network Hardware Architecture
IEEE Transactions on Neural Networks and Learning Systems, 2018Co-Authors: Jim Harkin, Liam P. Maguire, Liam J. Mcdaid, John J. WadeAbstract:Recent research has shown that a glial cell of astrocyte underpins a self-repair mechanism in the human brain, where spiking neurons provide direct and indirect feedbacks to presynaptic terminals. These feedbacks modulate the synaptic transmission probability of release (PR). When synaptic faults occur, the neuron becomes silent or near silent due to the low PR of synapses; whereby the PRs of remaining healthy synapses are then increased by the indirect feedback from the astrocyte cell. In this paper, a novel Hardware Architecture of Self-rePAiring spiking Neural NEtwoRk (SPANNER) is proposed, which mimics this self-repairing capability in the human brain. This paper demonstrates that the Hardware can self-detect and self-repair synaptic faults without the conventional components for the fault detection and fault repairing. Experimental results show that SPANNER can maintain the system performance with fault densities of up to 40%, and more importantly SPANNER has only a 20% performance degradation when the self-repairing Architecture is significantly damaged at a fault density of 80%.
Viktor Owall - One of the best experts on this subject based on the ideXlab platform.
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multicarrier faster than nyquist transceivers Hardware Architecture and performance analysis
IEEE Transactions on Circuits and Systems I-regular Papers, 2011Co-Authors: Deepak Dasalukunte, Fredrik Rusek, Viktor OwallAbstract:This paper evaluates the Hardware aspects of multicarrier faster-than-Nyquist (FTN) signaling transceivers. The choice of time-frequency spacing of the symbols in an FTN system for improved bandwidth efficiency is targeted towards efficient Hardware implementation. This work proposes a Hardware Architecture for the realization of iterative decoding of FTN multicarrier modulated signals. Compatibility with existing systems has been considered for smooth switching between the faster-than-Nyquist and orthogonal signaling schemes. One such being the use of fast Fourier transforms (FFTs) for multicarrier modulation. The performance of the fixed point model is very close to that of the floating point representation. The impact of system parameters such as number of projection points, time-frequency spacing, finite wordlengths and their design tradeoffs for reduced complexity iterative decoders in FTN systems have been investigated. The FTN decoder has been designed and synthesized in both 65 nm CMOS and FPGA. From the Hardware resource usage numbers it can be concluded that FTN signaling can be used to achieve higher bandwidth efficiency with acceptable complexity overhead.
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a Hardware Architecture for real time video segmentation utilizing memory reduction techniques
IEEE Transactions on Circuits and Systems for Video Technology, 2009Co-Authors: Hongtu Jiang, Hakan Ardo, Viktor OwallAbstract:This paper presents the implementation of a video segmentation unit used for embedded automated video surveillance systems. Various aspects of the underlying segmentation algorithm are explored and modifications are made with potential improvements of segmentation results and Hardware efficiency. In addition, to achieve real-time performance with high resolution video streams, a dedicated Hardware Architecture with streamlined dataflow and memory access reduction schemes are developed. The whole system is implemented on a Xilinx field-programmable gate array platform, capable of real-time segmentation with VGA resolution at 25 frames per second. Substantial memory bandwidth reduction of more than 70% is achieved by utilizing pixel locality as well as wordlength reduction. The Hardware platform is intended as a real-time testbench, especially for observations of long term effects with different parameter settings.
George A Constantinides - One of the best experts on this subject based on the ideXlab platform.
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a parallel Hardware Architecture for scale and rotation invariant feature detection
IEEE Transactions on Circuits and Systems for Video Technology, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper proposes a parallel Hardware Architecture for image feature detection based on the scale invariant feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific Hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed Architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320times240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several Hardware-orientated optimizations on performance, area and accuracy.
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a parallel Hardware Architecture for scale and rotation invariant feature detection
IEEE Transactions on Circuits and Systems for Video Technology, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper proposes a parallel Hardware Architecture for image feature detection based on the scale invariant feature transform algorithm and applied to the simultaneous localization and mapping problem. The work also proposes specific Hardware optimizations considered fundamental to embed such a robotic control system on-a-chip. The proposed Architecture is completely stand-alone; it reads the input data directly from a CMOS image sensor and provides the results via a field-programmable gate array coupled to an embedded processor. The results may either be used directly in an on-chip application or accessed through an Ethernet connection. The system is able to detect features up to 30 frames per second (320times240 pixels) and has accuracy similar to a PC-based implementation. The achieved system performance is at least one order of magnitude better than a PC-based solution, a result achieved by investigating the impact of several Hardware-orientated optimizations on performance, area and accuracy.
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a parallel Hardware Architecture for image feature detection
Applied Reconfigurable Computing, 2008Co-Authors: Vanderlei Bonato, Eduardo Marques, George A ConstantinidesAbstract:This paper presents a real time parallel Hardware Architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This Architecture receives as input a pixel stream read directly from a CMOS image sensor and produces as output the detected features, where each one is identified by their coordinates, scale and octave. In addition, the proposed Hardware also computes the orientation and gradient magnitude for every pixel of one image per octave, which is useful to generate the feature descriptors. This work also presents a suitable parameter set for Hardware implementation of the SIFT algorithm and proposes specific Hardware optimizations considered fundamental to embed whole system on a single chip, which implements in parallel 18 Gaussian filters, a modified CORDIC (COordinate Rotation DIgital Computer) algorithm version and a considerable number of fixed-point operations, such as those involved in a matrix inversion operation. As a result, the whole Architecture is able to process up to 30 frames per second for images of 320×240 pixels independent of the number of features.
Jaeho Nah - One of the best experts on this subject based on the ideXlab platform.
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raycore a ray tracing Hardware Architecture for mobile devices
ACM Transactions on Graphics, 2014Co-Authors: Jaeho Nah, Hyuckjoo Kwon, Dongseok Kim, Cheolho Jeong, Jinhong Park, Tackdon Han, Dinesh Manocha, Woochan ParkAbstract:We present RayCore, a mobile ray-tracing Hardware Architecture. RayCore facilitates high-quality rendering effects, such as reflection, refraction, and shadows, on mobile devices by performing real-time Whitted ray tracing. RayCore consists of two major components: ray-tracing units (RTUs) based on a unified traversal and intersection pipeline and a tree-building unit (TBU) for dynamic scenes. The overall RayCore Architecture offers considerable benefits in terms of die area, memory access, and power consumption. We have evaluated our Architecture based on FPGA and ASIC evaluations and demonstrate its performance on different benchmarks. According to the results, our Architecture demonstrates high performance per unit area and unit energy, making it highly suitable for use in mobile devices.
