The Experts below are selected from a list of 68265 Experts worldwide ranked by ideXlab platform
Yuke Wang - One of the best experts on this subject based on the ideXlab platform.
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low Hardware Complexity parallel turbo decoder architecture
International Symposium on Circuits and Systems, 2003Co-Authors: Zhongfeng Wang, Yiyan Tang, Yuke WangAbstract:Turbo decoders inherently have low throughput and long latency because of iterative decoding. Parallel processing is a powerful technique for high-throughput applications but often comes with large Hardware Complexity penalties. In this paper, we present a generic low Hardware Complexity parallel turbo decoder architecture, which enables multiple soft-input soft-output (SISO) decoders to process one data frame simultaneously. It can achieve multiple times the throughput of a typical serial decoder with a small fraction of Hardware overhead. The proposed architecture works for any type of random interleavers, which makes it extremely useful in practical applications where turbo interleave patterns are not free to design. Based on estimation, the illustrated low Hardware Complexity 2-level parallel turbo decoding architecture can achieve twice the throughput of a typical serial decoding architecture with less than 20% Hardware overhead when applied to 3rd generation CDMA systems.
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ISCAS (2) - Low Hardware Complexity parallel turbo decoder architecture
Proceedings of the 2003 International Symposium on Circuits and Systems 2003. ISCAS '03., 1Co-Authors: Zhongfeng Wang, Yiyan Tang, Yuke WangAbstract:Turbo decoders inherently have low throughput and long latency because of iterative decoding. Parallel processing is a powerful technique for high-throughput applications but often comes with large Hardware Complexity penalties. In this paper, we present a generic low Hardware Complexity parallel turbo decoder architecture, which enables multiple soft-input soft-output (SISO) decoders to process one data frame simultaneously. It can achieve multiple times the throughput of a typical serial decoder with a small fraction of Hardware overhead. The proposed architecture works for any type of random interleavers, which makes it extremely useful in practical applications where turbo interleave patterns are not free to design. Based on estimation, the illustrated low Hardware Complexity 2-level parallel turbo decoding architecture can achieve twice the throughput of a typical serial decoding architecture with less than 20% Hardware overhead when applied to 3rd generation CDMA systems.
Athanasios G. Kanatas - One of the best experts on this subject based on the ideXlab platform.
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Closed-loop beamspace MIMO systems with low Hardware Complexity
IEEE Vehicular Technology Conference, 2009Co-Authors: Vlasis Barousis, Antonis Kalis, Athanasios G. Kanatas, Constantinos B. PapadiasAbstract:Multiple input-multiple output (MIMO) systems have drawn remarkable interest in recent years, since they are known to boost the spectral efficiency of wireless communication systems compared to single antenna architectures. However, the implementation cost and circuit Complexity of such systems conflicts the guaranteed high performance gain. Recent research efforts focus on the investigation of cheaper and low Complexity transceivers, introducing a novel beamspace MIMO (BS-MIMO) architecture. BS-MIMO systems have shown equivalent performance with the corresponding conventional systems, while they have been also evaluated in closed loop environments. In this paper we extend the closed loop BS MIMO approach presenting advanced limited feedback techniques which outperform predecessor feedback schemes.
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Reducing Hardware Complexity of MIMO Systems with Antenna Subarray Formation
2nd European Conference on Antennas and Propagation (EuCAP 2007), 2007Co-Authors: Panagiotis Theofilakos, Athanasios G. KanatasAbstract:Antenna subarray formation (ASF) is an alternative to antenna selection technique that reduces the Hardware Complexity of MIMO systems with a minor performance penalty with respect to the full-Complexity system. With this method, each RF chain is not allocated to a single antenna element, but to a complex-weighted and combined response of a subarray of the available antenna elements. In this paper we compare the capacity performance of several analytical algorithms for receive ASF and present theoretical upper bounds on the ergodic capacity of the proposed technique for Rayleigh i.i.d. channels. (6 pages)
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reduced Hardware Complexity receive antenna subarray formation for mimo systems based on frobenius norm criterion
International Symposium on Wireless Communication Systems, 2006Co-Authors: Panagiotis Theofilakos, Athanasios G. KanatasAbstract:Antenna subarray formation (ASF) has been recently proposed as an alternative method to Antenna Selection that reduces Hardware Complexity while offering increased data rates. With this method each RF chain is not allocated to a single element but instead to the combined and weighted output of a subarray of elements. In this paper, we remove the restriction that each antenna element must participate in only one subarray and study the capacity performance when a given number of phase shifters and variable gain amplifiers are available at the receiver. To further reduce the Hardware Complexity, we introduce a version that discards the variable gain amplifiers. A fast and efficient algorithm for ASF is used, which offers remarkably high data rates while maintaining low Hardware and computational Complexity.
Mahsa Shoaran - One of the best experts on this subject based on the ideXlab platform.
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Hardware Complexity analysis of deep neural networks and decision tree ensembles for real time neural data classification
International IEEE EMBS Conference on Neural Engineering, 2019Co-Authors: Milad Taghavi, Mahsa ShoaranAbstract:A fast and low-power embedded classifier with small footprint is essential for real-time applications such as brain-machine interfaces (BMIs) and closed-loop neuromodulation for neurological disorders. In most applications with large datasets of unstructured data, such as images, deep neural networks (DNNs) achieve a remarkable classification accuracy. However, DNN models impose a high computational cost during inference, and are not necessarily ideal for problems with limited training sets. The computationally intensive nature of deep models may also degrade the classification latency, that is critical for real-time closed-loop applications. Among other methods, ensembles of decision trees (DTs) have recently been very successful in neural data classification tasks. DTs can be designed to successively process a limited number of features during inference, and thus impose much lower computational and memory overhead. Here, we compare the Hardware Complexity of DNNs and gradient boosted DTs for classification of real-time electrophysiological data in epilepsy. Our analysis shows that the strict energy-area-latency trade-off can be relaxed using an ensemble of DTs, and they can be significantly more efficient than alternative DNN models, while achieving better classification accuracy in real-time neural data classification tasks.
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NER - Hardware Complexity Analysis of Deep Neural Networks and Decision Tree Ensembles for Real-time Neural Data Classification
2019 9th International IEEE EMBS Conference on Neural Engineering (NER), 2019Co-Authors: Milad Taghavi, Mahsa ShoaranAbstract:A fast and low-power embedded classifier with small footprint is essential for real-time applications such as brain-machine interfaces (BMIs) and closed-loop neuromodulation for neurological disorders. In most applications with large datasets of unstructured data, such as images, deep neural networks (DNNs) achieve a remarkable classification accuracy. However, DNN models impose a high computational cost during inference, and are not necessarily ideal for problems with limited training sets. The computationally intensive nature of deep models may also degrade the classification latency, that is critical for real-time closed-loop applications. Among other methods, ensembles of decision trees (DTs) have recently been very successful in neural data classification tasks. DTs can be designed to successively process a limited number of features during inference, and thus impose much lower computational and memory overhead. Here, we compare the Hardware Complexity of DNNs and gradient boosted DTs for classification of real-time electrophysiological data in epilepsy. Our analysis shows that the strict energy-area-latency trade-off can be relaxed using an ensemble of DTs, and they can be significantly more efficient than alternative DNN models, while achieving better classification accuracy in real-time neural data classification tasks.
Paul P Sotiriadis - One of the best experts on this subject based on the ideXlab platform.
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comparison of recently developed single bit all digital frequency synthesizers in terms of Hardware Complexity and performance
International Symposium on Circuits and Systems, 2018Co-Authors: Charis Basetas, Nikos Temenos, Paul P SotiriadisAbstract:Internet of Things growth requires the development of low power and low cost wireless transceivers. Here, we present three recently developed all-digital frequency synthesizer architectures which can be used as transmitters for Internet of Things applications. These all-digital transmitters are based on different sigma-delta modulator architectures, varying in performance and Hardware Complexity. The operation principles of the three proposed architectures are described. Then, proof-of-concept FPGA implementations of these architectures are presented and compared in terms of Hardware resources and speed. Their performance is tested using 32-QAM modulated signals. Finally, conclusions are drawn to help the reader select the most suitable architecture for a given application.
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ISCAS - Comparison of Recently Developed Single-Bit All-Digital Frequency Synthesizers in Terms of Hardware Complexity and Performance
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018Co-Authors: Charis Basetas, Nikos Temenos, Paul P SotiriadisAbstract:Internet of Things growth requires the development of low power and low cost wireless transceivers. Here, we present three recently developed all-digital frequency synthesizer architectures which can be used as transmitters for Internet of Things applications. These all-digital transmitters are based on different sigma-delta modulator architectures, varying in performance and Hardware Complexity. The operation principles of the three proposed architectures are described. Then, proof-of-concept FPGA implementations of these architectures are presented and compared in terms of Hardware resources and speed. Their performance is tested using 32-QAM modulated signals. Finally, conclusions are drawn to help the reader select the most suitable architecture for a given application.
Zhongfeng Wang - One of the best experts on this subject based on the ideXlab platform.
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low Hardware Complexity parallel turbo decoder architecture
International Symposium on Circuits and Systems, 2003Co-Authors: Zhongfeng Wang, Yiyan Tang, Yuke WangAbstract:Turbo decoders inherently have low throughput and long latency because of iterative decoding. Parallel processing is a powerful technique for high-throughput applications but often comes with large Hardware Complexity penalties. In this paper, we present a generic low Hardware Complexity parallel turbo decoder architecture, which enables multiple soft-input soft-output (SISO) decoders to process one data frame simultaneously. It can achieve multiple times the throughput of a typical serial decoder with a small fraction of Hardware overhead. The proposed architecture works for any type of random interleavers, which makes it extremely useful in practical applications where turbo interleave patterns are not free to design. Based on estimation, the illustrated low Hardware Complexity 2-level parallel turbo decoding architecture can achieve twice the throughput of a typical serial decoding architecture with less than 20% Hardware overhead when applied to 3rd generation CDMA systems.
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ISCAS (2) - Low Hardware Complexity parallel turbo decoder architecture
Proceedings of the 2003 International Symposium on Circuits and Systems 2003. ISCAS '03., 1Co-Authors: Zhongfeng Wang, Yiyan Tang, Yuke WangAbstract:Turbo decoders inherently have low throughput and long latency because of iterative decoding. Parallel processing is a powerful technique for high-throughput applications but often comes with large Hardware Complexity penalties. In this paper, we present a generic low Hardware Complexity parallel turbo decoder architecture, which enables multiple soft-input soft-output (SISO) decoders to process one data frame simultaneously. It can achieve multiple times the throughput of a typical serial decoder with a small fraction of Hardware overhead. The proposed architecture works for any type of random interleavers, which makes it extremely useful in practical applications where turbo interleave patterns are not free to design. Based on estimation, the illustrated low Hardware Complexity 2-level parallel turbo decoding architecture can achieve twice the throughput of a typical serial decoding architecture with less than 20% Hardware overhead when applied to 3rd generation CDMA systems.
