The Experts below are selected from a list of 318 Experts worldwide ranked by ideXlab platform
Kyle Johnsen - One of the best experts on this subject based on the ideXlab platform.
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ubiquitous collaborative activity virtual environments
Conference on Computer Supported Cooperative Work, 2012Co-Authors: Aryabrata Basu, Andrew Raij, Kyle JohnsenAbstract:We introduce a new paradigm of collaborative computing called the Ubiquitous Collaborative Activity Virtual Environment (UCAVE). UCAVEs are portable immersive virtual environments that leverage mobile communication platforms, motion trackers and displays to facilitate ad-hoc virtual collaboration. We discuss design criteria and research challenges for UCAVEs, as well as a prototype Hardware Configuration that enables UCAVE interactions using modern smart phones and head mounted displays.
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CSCW - Ubiquitous collaborative activity virtual environments
Proceedings of the ACM 2012 conference on Computer Supported Cooperative Work - CSCW '12, 2012Co-Authors: Aryabrata Basu, Andrew Raij, Kyle JohnsenAbstract:We introduce a new paradigm of collaborative computing called the Ubiquitous Collaborative Activity Virtual Environment (UCAVE). UCAVEs are portable immersive virtual environments that leverage mobile communication platforms, motion trackers and displays to facilitate ad-hoc virtual collaboration. We discuss design criteria and research challenges for UCAVEs, as well as a prototype Hardware Configuration that enables UCAVE interactions using modern smart phones and head mounted displays.
Aryabrata Basu - One of the best experts on this subject based on the ideXlab platform.
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ubiquitous collaborative activity virtual environments
Conference on Computer Supported Cooperative Work, 2012Co-Authors: Aryabrata Basu, Andrew Raij, Kyle JohnsenAbstract:We introduce a new paradigm of collaborative computing called the Ubiquitous Collaborative Activity Virtual Environment (UCAVE). UCAVEs are portable immersive virtual environments that leverage mobile communication platforms, motion trackers and displays to facilitate ad-hoc virtual collaboration. We discuss design criteria and research challenges for UCAVEs, as well as a prototype Hardware Configuration that enables UCAVE interactions using modern smart phones and head mounted displays.
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CSCW - Ubiquitous collaborative activity virtual environments
Proceedings of the ACM 2012 conference on Computer Supported Cooperative Work - CSCW '12, 2012Co-Authors: Aryabrata Basu, Andrew Raij, Kyle JohnsenAbstract:We introduce a new paradigm of collaborative computing called the Ubiquitous Collaborative Activity Virtual Environment (UCAVE). UCAVEs are portable immersive virtual environments that leverage mobile communication platforms, motion trackers and displays to facilitate ad-hoc virtual collaboration. We discuss design criteria and research challenges for UCAVEs, as well as a prototype Hardware Configuration that enables UCAVE interactions using modern smart phones and head mounted displays.
Andrew Raij - One of the best experts on this subject based on the ideXlab platform.
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ubiquitous collaborative activity virtual environments
Conference on Computer Supported Cooperative Work, 2012Co-Authors: Aryabrata Basu, Andrew Raij, Kyle JohnsenAbstract:We introduce a new paradigm of collaborative computing called the Ubiquitous Collaborative Activity Virtual Environment (UCAVE). UCAVEs are portable immersive virtual environments that leverage mobile communication platforms, motion trackers and displays to facilitate ad-hoc virtual collaboration. We discuss design criteria and research challenges for UCAVEs, as well as a prototype Hardware Configuration that enables UCAVE interactions using modern smart phones and head mounted displays.
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CSCW - Ubiquitous collaborative activity virtual environments
Proceedings of the ACM 2012 conference on Computer Supported Cooperative Work - CSCW '12, 2012Co-Authors: Aryabrata Basu, Andrew Raij, Kyle JohnsenAbstract:We introduce a new paradigm of collaborative computing called the Ubiquitous Collaborative Activity Virtual Environment (UCAVE). UCAVEs are portable immersive virtual environments that leverage mobile communication platforms, motion trackers and displays to facilitate ad-hoc virtual collaboration. We discuss design criteria and research challenges for UCAVEs, as well as a prototype Hardware Configuration that enables UCAVE interactions using modern smart phones and head mounted displays.
Stamatis Vassiliadis - One of the best experts on this subject based on the ideXlab platform.
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interprocedural compiler optimization for partial run time reConfiguration
Signal Processing Systems, 2006Co-Authors: Elena Moscu Panainte, Koen Bertels, Stamatis VassiliadisAbstract:In this paper, we study the performance impact of dynamic Hardware reConfigurations for current reconfigurable technology. As a testbed, we target the Xilinx Virtex II Pro, the Molen experimental platform and the MPEG2 encoder as the application. Our experiments show that slowdowns of up to a factor 1000 are observed when the Configuration latency is not hidden by the compiler. In order to avoid the performance decrease, we propose an interprocedural optimization that minimizes the number of executed Hardware Configuration instructions taking into account constraints such as the "FPGA-area placement conflicts" between the available Hardware Configurations. The presented algorithm allows the anticipation of Hardware Configuration instructions up to the application's main procedure. The presented results show that our optimization produces a reduction of 3 to 5 order of magnitude of the number of executed Hardware Configuration instructions. Moreover, the optimization allows to exploit up to 97% of the maximal theoretical speedup achieved by the reconfigurable Hardware execution.
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SAMOS - Interprocedural optimization for dynamic Hardware Configurations
Lecture Notes in Computer Science, 2005Co-Authors: Elena Moscu Panainte, Koen Bertels, Stamatis VassiliadisAbstract:Little research in compiler optimizations has been undertaken to eliminate or diminish the negative influence on performance of the huge reConfiguration latency of the available FPGA platforms. In this paper, we propose an interprocedural optimization that minimizes the number of executed Hardware Configuration instructions taking into account constraints such as the ”FPGA-area placement conflicts” between the available Hardware Configurations. The proposed algorithm allows the anticipation of Hardware Configuration instructions up to the application's main procedure. The presented results show that our optimization produces a reduction of up to 3 – 5 order of magnitude of the number of executed Hardware Configuration instructions.
Koen Bertels - One of the best experts on this subject based on the ideXlab platform.
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runtime task mapping based on Hardware Configuration reuse
Reconfigurable Computing and FPGAs, 2010Co-Authors: Kamana Sigdel, Koen Bertels, Carlo Galuzzi, Mark Thompson, Andy D PimentelAbstract:In this paper, we propose a new heuristic for runtime task mapping of application(s) onto reconfigurable architectures. The heuristic is based on Hardware Configuration reuse, which tries to avoid the reConfiguration overhead of few selected tasks, by reusing the Hardware Configurations already available in the reconfigurable Hardware. We evaluate our heuristic by performing a mapping of an extended Motion-JPEG application onto a reconfigurable architecture. A large variety of experiments have been conducted on the proposed algorithm for the same reconfigurable architecture model with different FPGA sizes. The obtained result shows up to 45\% performance gain by reusing the Hardware Configurations as suggested by the proposed heuristic, compared to well-known approaches from the state-of-the-art, which do not take into consideration the Hardware Configuration reuse.
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ReConFig - Runtime Task Mapping Based on Hardware Configuration Reuse
2010 International Conference on Reconfigurable Computing and FPGAs, 2010Co-Authors: Kamana Sigdel, Koen Bertels, Carlo Galuzzi, Mark Thompson, Andy D PimentelAbstract:In this paper, we propose a new heuristic for runtime task mapping of application(s) onto reconfigurable architectures. The heuristic is based on Hardware Configuration reuse, which tries to avoid the reConfiguration overhead of few selected tasks, by reusing the Hardware Configurations already available in the reconfigurable Hardware. We evaluate our heuristic by performing a mapping of an extended Motion-JPEG application onto a reconfigurable architecture. A large variety of experiments have been conducted on the proposed algorithm for the same reconfigurable architecture model with different FPGA sizes. The obtained result shows up to 45\% performance gain by reusing the Hardware Configurations as suggested by the proposed heuristic, compared to well-known approaches from the state-of-the-art, which do not take into consideration the Hardware Configuration reuse.
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interprocedural compiler optimization for partial run time reConfiguration
Signal Processing Systems, 2006Co-Authors: Elena Moscu Panainte, Koen Bertels, Stamatis VassiliadisAbstract:In this paper, we study the performance impact of dynamic Hardware reConfigurations for current reconfigurable technology. As a testbed, we target the Xilinx Virtex II Pro, the Molen experimental platform and the MPEG2 encoder as the application. Our experiments show that slowdowns of up to a factor 1000 are observed when the Configuration latency is not hidden by the compiler. In order to avoid the performance decrease, we propose an interprocedural optimization that minimizes the number of executed Hardware Configuration instructions taking into account constraints such as the "FPGA-area placement conflicts" between the available Hardware Configurations. The presented algorithm allows the anticipation of Hardware Configuration instructions up to the application's main procedure. The presented results show that our optimization produces a reduction of 3 to 5 order of magnitude of the number of executed Hardware Configuration instructions. Moreover, the optimization allows to exploit up to 97% of the maximal theoretical speedup achieved by the reconfigurable Hardware execution.
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SAMOS - Interprocedural optimization for dynamic Hardware Configurations
Lecture Notes in Computer Science, 2005Co-Authors: Elena Moscu Panainte, Koen Bertels, Stamatis VassiliadisAbstract:Little research in compiler optimizations has been undertaken to eliminate or diminish the negative influence on performance of the huge reConfiguration latency of the available FPGA platforms. In this paper, we propose an interprocedural optimization that minimizes the number of executed Hardware Configuration instructions taking into account constraints such as the ”FPGA-area placement conflicts” between the available Hardware Configurations. The proposed algorithm allows the anticipation of Hardware Configuration instructions up to the application's main procedure. The presented results show that our optimization produces a reduction of up to 3 – 5 order of magnitude of the number of executed Hardware Configuration instructions.
