The Experts below are selected from a list of 37632 Experts worldwide ranked by ideXlab platform
Gregory R Ganger - One of the best experts on this subject based on the ideXlab platform.
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tvarak software managed Hardware offload for redundancy in direct access nvm storage
International Symposium on Computer Architecture, 2020Co-Authors: Rajat Kateja, Nathan Beckmann, Gregory R GangerAbstract:Production storage systems complement device-level ECC (which covers media errors) with system-checksums and cross-device parity. This system-level redundancy enables systems to detect and recover from data corruption due to device firmware bugs (e.g., reading data from the wrong physical location). Direct access to NVM penalizes software-only implementations of system-level redundancy, forcing a choice between lack of data protection or significant performance penalties. We propose to offload the update and verification of system-level redundancy to Tvarak, a new Hardware Controller co-located with the last-level cache. Tvarak enables efficient protection of data from such bugs in memory Controller and NVM DIMM firmware. Simulation-based evaluation with seven data-intensive applications shows that Tvarak is efficient. For example, Tvarak reduces Redis set-only performance by only 3%, compared to 50% reduction for a state-of-the-art software-only approach.
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tvarak software managed Hardware offload for dax nvm storage redundancy
arXiv: Hardware Architecture, 2019Co-Authors: Rajat Kateja, Nathan Beckmann, Gregory R GangerAbstract:Tvarak efficiently implements system-level redundancy for direct-access (DAX) NVM storage. Production storage systems complement device-level ECC (which covers media errors) with system-checksums and cross-device parity. This system-level redundancy enables detection of and recovery from data corruption due to device firmware bugs (e.g., reading data from the wrong physical location). Direct access to NVM penalizes software-only implementations of system-level redundancy, forcing a choice between lack of data protection or significant performance penalties. Offloading the update and verification of system-level redundancy to Tvarak, a Hardware Controller co-located with the last-level cache, enables efficient protection of data from such bugs in memory Controller and NVM DIMM firmware. Simulation-based evaluation with seven data-intensive applications shows Tvarak's performance and energy efficiency. For example, Tvarak reduces Redis set-only performance by only 3%, compared to 50% reduction for a state-of-the-art software-only approach.
Tomoki Yokoyama - One of the best experts on this subject based on the ideXlab platform.
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variable carrier frequency deadbeat control with hysteresis band using soc fpga for utility interactive inverter
European Conference on Power Electronics and Applications, 2013Co-Authors: Morito Yoshida, Tomoki YokoyamaAbstract:Using SoC-FPGA based Hardware Controller, the real time gain calculation of deadbeat control can be realized, which result in the realization of variable carrier frequency control of PWM inverter for utility interactive system based on deadbeat control. Precise current control with adjustable hysteresis band was realized with the calculation capability of Soc-FPGA. It is verified that the control accuracy and the efficiency of the inverter can be adjustable.
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high performance fpga Controller for digital control of power electronics applications
International Power Electronics and Motion Control Conference, 2009Co-Authors: Kazuki Sugahara, Shinsuke Oida, Tomoki YokoyamaAbstract:Recently, progress of PLD (Programmable Logic Device) like FPGA or CPLD makes it realize the digital control system of power electronics without microprocessor (CPU or DSP). Complex control algorithm can be implemented into FPGA and the calculation time can be dramatically reduced based on parallel processing Hardware circuit. But commercial based Controller board for power electronics is mainly designed based on DSP or CPU. In this paper, design concept of original FPGA based Controller for power electronics is proposed. Cyclone III with 24k LEs(logic elements) is adopted as FPGA device, and 1MHz A/D converter with 8ch multiplexer, 2MHz D/A converter with 8ch multiplexer, 12×4 digital I/O (3.3V/5.0V), 40 digital I/O(3.3V), RS-232C I/F, SD card slot and ethernet I/F are implemented. Expansion A/D and D/A board are also designed to expand the high speed controllability. The proposed FPGA based Controller can be widely applied to many power electronics applications. Demonstration of experimental result with 1MHz high speed sampling digital control method was realized, the advantages of FPGA based Hardware Controller is indicated.
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verification of an autonomous decentralized ups system with fast transient response using a fpga based Hardware Controller
Journal of Power Electronics, 2009Co-Authors: Tomoki Yokoyama, Nobuaki Doi, Toshiya IshiokaAbstract:This paper proposes an autonomous decentralized control for a parallel connected uninterruptible power supply (UPS) system based on a fast power detection method using a FPGA based Hardware Controller for a single phase system. Each UPS unit detects only its output voltage and current without communications signal exchange and a quasi dq transformation method is applied to detect the phase and amplitude of the output voltage and the output current for the single phase system. Fast power detection can be achieved based on a quasi dq transformation, which results in a realization of very fast transient response under rapid load change. In the proposed method, the entire control system is implemented in one FPGA chip. Complicated calculations are assigned to Hardware calculation logic, and the parallel processing circuit makes it possible to realize minimized calculation time. Also, an Nios II CPU core is implemented in the same FPGA chip, and the software can be applied for non-time critical calculations. Applying this control system, an autonomous decentralized UPS system with very fast transient response is realized. Feasibility and stable operation are confirmed by means of an experimental setup with three UPSs connected in parallel. Also, rapid load change is applied and excellent performance of the system is confirmed in terms of transient response and stability.
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variable sampling quasi multirate deadbeat control method for single phase pwm inverter in low carrier frequency
Power Conversion Conference, 2007Co-Authors: S Tahara, T Fujii, Tomoki YokoyamaAbstract:A new approach for real time digital feedback control of PWM inverter is proposed, in which a quasi multi-rate deadbeat control combined with variable sampling method using FPGA based Hardware Controller. It was reported that the deadbeat control method with FPGA based Hardware Controller had the very good transient response for various loads, but these reports were mainly focused on a few KW class PWM inverter system, so the high carrier frequency were adopted. But in MW class PWM inverter system, the carrier frequency is limited up to 2 kHz range, because of the performance of the switching devices and the trade off against the efficiency of the inverter. In this condition, the controllability of the PWM inverter is not so much expected. In the proposed method, to ensure the tracking accuracy of the output voltage to the reference voltage, more than two sampled data is used while one carrier interval. The control characteristics of the proposed variable sampling deadbeat control is verified through simulations and experiments.
Matti Hamalainen - One of the best experts on this subject based on the ideXlab platform.
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versatile synchronized real time meg Hardware Controller for large scale fast data acquisition
Review of Scientific Instruments, 2017Co-Authors: Limin Sun, Menglai Han, Kevin Pratt, D N Paulson, Christoph Dinh, Lorenz Esch, Yoshio Okada, Matti HamalainenAbstract:Versatile Controllers for accurate, fast, and real-time synchronized acquisition of large-scale data are useful in many areas of science, engineering, and technology. Here, we describe the development of a Controller software based on a technique called queued state machine for controlling the data acquisition (DAQ) Hardware, continuously acquiring a large amount of data synchronized across a large number of channels (>400) at a fast rate (up to 20 kHz/channel) in real time, and interfacing with applications for real-time data analysis and display of electrophysiological data. This DAQ Controller was developed specifically for a 384-channel pediatric whole-head magnetoencephalography (MEG) system, but its architecture is useful for wide applications. This Controller running in a LabVIEW environment interfaces with microprocessors in the MEG sensor electronics to control their real-time operation. It also interfaces with a real-time MEG analysis software via transmission control protocol/internet protocol, to control the synchronous acquisition and transfer of the data in real time from >400 channels to acquisition and analysis workstations. The successful implementation of this Controller for an MEG system with a large number of channels demonstrates the feasibility of employing the present architecture in several other applications.
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versatile synchronized real time meg Hardware Controller for large scale fast data acquisition
Review of Scientific Instruments, 2017Co-Authors: Kevin Pratt, D N Paulson, Christoph Dinh, Lorenz Esch, Yoshio Okada, Matti HamalainenAbstract:Versatile Controllers for accurate, fast, and real-time synchronized acquisition of large-scale data are useful in many areas of science, engineering, and technology. Here, we describe the development of a Controller software based on a technique called queued state machine for controlling the data acquisition (DAQ) Hardware, continuously acquiring a large amount of data synchronized across a large number of channels (>400) at a fast rate (up to 20 kHz/channel) in real time, and interfacing with applications for real-time data analysis and display of electrophysiological data. This DAQ Controller was developed specifically for a 384-channel pediatric whole-head magnetoencephalography (MEG) system, but its architecture is useful for wide applications. This Controller running in a LabVIEW environment interfaces with microprocessors in the MEG sensor electronics to control their real-time operation. It also interfaces with a real-time MEG analysis software via transmission control protocol/internet protocol,...
Rajat Kateja - One of the best experts on this subject based on the ideXlab platform.
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tvarak software managed Hardware offload for redundancy in direct access nvm storage
International Symposium on Computer Architecture, 2020Co-Authors: Rajat Kateja, Nathan Beckmann, Gregory R GangerAbstract:Production storage systems complement device-level ECC (which covers media errors) with system-checksums and cross-device parity. This system-level redundancy enables systems to detect and recover from data corruption due to device firmware bugs (e.g., reading data from the wrong physical location). Direct access to NVM penalizes software-only implementations of system-level redundancy, forcing a choice between lack of data protection or significant performance penalties. We propose to offload the update and verification of system-level redundancy to Tvarak, a new Hardware Controller co-located with the last-level cache. Tvarak enables efficient protection of data from such bugs in memory Controller and NVM DIMM firmware. Simulation-based evaluation with seven data-intensive applications shows that Tvarak is efficient. For example, Tvarak reduces Redis set-only performance by only 3%, compared to 50% reduction for a state-of-the-art software-only approach.
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tvarak software managed Hardware offload for dax nvm storage redundancy
arXiv: Hardware Architecture, 2019Co-Authors: Rajat Kateja, Nathan Beckmann, Gregory R GangerAbstract:Tvarak efficiently implements system-level redundancy for direct-access (DAX) NVM storage. Production storage systems complement device-level ECC (which covers media errors) with system-checksums and cross-device parity. This system-level redundancy enables detection of and recovery from data corruption due to device firmware bugs (e.g., reading data from the wrong physical location). Direct access to NVM penalizes software-only implementations of system-level redundancy, forcing a choice between lack of data protection or significant performance penalties. Offloading the update and verification of system-level redundancy to Tvarak, a Hardware Controller co-located with the last-level cache, enables efficient protection of data from such bugs in memory Controller and NVM DIMM firmware. Simulation-based evaluation with seven data-intensive applications shows Tvarak's performance and energy efficiency. For example, Tvarak reduces Redis set-only performance by only 3%, compared to 50% reduction for a state-of-the-art software-only approach.
Ramaswamy Arulmozhiyal - One of the best experts on this subject based on the ideXlab platform.
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Research Article Modeling and Simulation of Control Actuation System with Fuzzy-PID Logic Controlled Brushless Motor Drives for Missiles Glider Applications
2016Co-Authors: Murali Muniraj, Ramaswamy ArulmozhiyalAbstract:Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. A control actuation system has been used extensively in automotive, aerospace, and defense applications. The major challenges in modeling control actuation system are rise time, maximum peak to peak overshoot, and response to nonlinear system with percentage error. This paper addresses the challenges in modeling and real time implementation of control actuation system for missiles glider applications. As an alternative fuzzy-PID Controller is proposed inBLDCmotor drive followed by linkagemechanism to actuate fins in missiles and gliders. The proposed system will realize better rise time and less overshoot while operating in extreme nonlinear dynamic system conditions. Amathematical model of BLDCmotor is derived in state space form.The complete control actuation system is modeled in MATLAB/Simulink environment and verified by performing simulation studies. A real time prototype of the control actuation is developed with dSPACE-1104 Hardware Controller and a detailed analysis is carried out to confirm the viability of the proposed system. 1
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Modeling and Simulation of Control Actuation System with Fuzzy-PID Logic Controlled Brushless Motor Drives for Missiles Glider Applications.
TheScientificWorldJournal, 2015Co-Authors: Murali Muniraj, Ramaswamy ArulmozhiyalAbstract:A control actuation system has been used extensively in automotive, aerospace, and defense applications. The major challenges in modeling control actuation system are rise time, maximum peak to peak overshoot, and response to nonlinear system with percentage error. This paper addresses the challenges in modeling and real time implementation of control actuation system for missiles glider applications. As an alternative fuzzy-PID Controller is proposed in BLDC motor drive followed by linkage mechanism to actuate fins in missiles and gliders. The proposed system will realize better rise time and less overshoot while operating in extreme nonlinear dynamic system conditions. A mathematical model of BLDC motor is derived in state space form. The complete control actuation system is modeled in MATLAB/Simulink environment and verified by performing simulation studies. A real time prototype of the control actuation is developed with dSPACE-1104 Hardware Controller and a detailed analysis is carried out to confirm the viability of the proposed system.
