The Experts below are selected from a list of 84 Experts worldwide ranked by ideXlab platform
Nabil F. Kerkiz - One of the best experts on this subject based on the ideXlab platform.
-
ICECS - Netlist partitioning method suitable for adaptive computing systems
2013 IEEE 20th International Conference on Electronics Circuits and Systems (ICECS), 2013Co-Authors: Nabil F. Kerkiz, Amr ElchouemiAbstract:Adaptive computing systems (ACSs) are flexible Hardware accelerators for applications in domains such as image and digital signal processing. However, the mapping of applications onto ACSs using the traditional methods can take long time for a Hardware Engineer to develop and debug. A software design environment called CHAMPION was developed at the University of Tennessee to enable the automated mapping of applications onto ACSs. In this paper the compilation path of CHAMPION is described and a new recursive partitioning method based on topological ordering and levelization (RPL) is presented. The proposed method performs multi-FPGA partitioning by taking into account six different partitioning constraints.
-
Netlist partitioning method suitable for adaptive computing systems
2013 IEEE 20th International Conference on Electronics Circuits and Systems (ICECS), 2013Co-Authors: Nabil F. Kerkiz, Amr ElchouemiAbstract:Adaptive computing systems (ACSs) are flexible Hardware accelerators for applications in domains such as image and digital signal processing. However, the mapping of applications onto ACSs using the traditional methods can take long time for a Hardware Engineer to develop and debug. A software design environment called CHAMPION was developed at the University of Tennessee to enable the automated mapping of applications onto ACSs. In this paper the compilation path of CHAMPION is described and a new recursive partitioning method based on topological ordering and levelization (RPL) is presented. The proposed method performs multi-FPGA partitioning by taking into account six different partitioning constraints.
-
FCCM - Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems
2001Co-Authors: Nabil F. Kerkiz, B. Srijanto, M. Langston, D. Newport, D. BouldinAbstract:Adaptive computing systems (ACSs) can serve as flexible Hardware accelerators for applications in domains such as image and digital signal processing. However, the mapping of applications onto ACSs using the traditional methods can take months for a Hardware Engineer to develop and debug. To enable application designers to map their applications automatically onto ACSs, a software design environment called CHAMPION was developed at the University of Tennessee. This environment permits high-level design entry using the Cantata graphical programming environment from KRI and hides from the user the low-level details of the Hardware architecture. Thus, ACSs can be utilized by a wider audience and application development can be accomplished in less time. Furthermore, CHAMPION provides the means to map onto multiple ACS platforms, thereby exploiting rapid advances being made in Hardware.
-
Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems
The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01), 2001Co-Authors: Nabil F. Kerkiz, B. Srijanto, M. Langston, D. Newport, D. BouldinAbstract:Adaptive computing systems (ACSs) can serve as flexible Hardware accelerators for applications in domains such as image and digital signal processing. However, the mapping of applications onto ACSs using the traditional methods can take months for a Hardware Engineer to develop and debug. To enable application designers to map their applications automatically onto ACSs, a software design environment called CHAMPION was developed at the University of Tennessee. This environment permits high-level design entry using the Cantata graphical programming environment from KRI and hides from the user the low-level details of the Hardware architecture. Thus, ACSs can be utilized by a wider audience and application development can be accomplished in less time. Furthermore, CHAMPION provides the means to map onto multiple ACS platforms, thereby exploiting rapid advances being made in Hardware.
Dorian Sabaz - One of the best experts on this subject based on the ideXlab platform.
-
Embedded Linux for concurrent dynamic partially reconfigurable FPGA systems
2012 NASA ESA Conference on Adaptive Hardware and Systems (AHS), 2012Co-Authors: Victor Gusev Lesau, Edward Chen, William A. Gruver, Dorian SabazAbstract:Dynamic Partial Reconfiguration (DPR) of Field Programmable Gate Arrays (FPGAs) is a technology that enables the development of embedded systems with hot swappable logic on the FPGA fabric. This means that Hardware logic can be swapped in and out on-the-fly while the rest of the system is operational. Since DPR is relatively new, tool support is still evolving. This paper introduces new FPGA architectural tools and Linux OS modifications that aid in supporting DPR on FPGAs for control. We emphasize that control systems benefit from real Hardware concurrency, meaning that by moving the control intelligence into Hardware we minimize the negative effects inherent to threads and their scheduler. This leaves software with the role of a high-level administrator rather than an executor, thus eliminating unnecessary bottlenecks. The developed tools enable the Hardware Engineer to develop DPR-FPGA systems more effectively for rapid control system development.
-
AHS - Embedded Linux for concurrent dynamic partially reconfigurable FPGA systems
2012 NASA ESA Conference on Adaptive Hardware and Systems (AHS), 2012Co-Authors: Victor Gusev Lesau, Edward Chen, William A. Gruver, Dorian SabazAbstract:Dynamic Partial Reconfiguration (DPR) of Field Programmable Gate Arrays (FPGAs) is a technology that enables the development of embedded systems with hot swappable logic on the FPGA fabric. This means that Hardware logic can be swapped in and out on-the-fly while the rest of the system is operational. Since DPR is relatively new, tool support is still evolving. This paper introduces new FPGA architectural tools and Linux OS modifications that aid in supporting DPR on FPGAs for control. We emphasize that control systems benefit from real Hardware concurrency, meaning that by moving the control intelligence into Hardware we minimize the negative effects inherent to threads and their scheduler. This leaves software with the role of a high-level administrator rather than an executor, thus eliminating unnecessary bottlenecks. The developed tools enable the Hardware Engineer to develop DPR-FPGA systems more effectively for rapid control system development.
D. Bouldin - One of the best experts on this subject based on the ideXlab platform.
-
FCCM - Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems
2001Co-Authors: Nabil F. Kerkiz, B. Srijanto, M. Langston, D. Newport, D. BouldinAbstract:Adaptive computing systems (ACSs) can serve as flexible Hardware accelerators for applications in domains such as image and digital signal processing. However, the mapping of applications onto ACSs using the traditional methods can take months for a Hardware Engineer to develop and debug. To enable application designers to map their applications automatically onto ACSs, a software design environment called CHAMPION was developed at the University of Tennessee. This environment permits high-level design entry using the Cantata graphical programming environment from KRI and hides from the user the low-level details of the Hardware architecture. Thus, ACSs can be utilized by a wider audience and application development can be accomplished in less time. Furthermore, CHAMPION provides the means to map onto multiple ACS platforms, thereby exploiting rapid advances being made in Hardware.
-
Automatic Mapping of Multiple Applications to Multiple Adaptive Computing Systems
The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01), 2001Co-Authors: Nabil F. Kerkiz, B. Srijanto, M. Langston, D. Newport, D. BouldinAbstract:Adaptive computing systems (ACSs) can serve as flexible Hardware accelerators for applications in domains such as image and digital signal processing. However, the mapping of applications onto ACSs using the traditional methods can take months for a Hardware Engineer to develop and debug. To enable application designers to map their applications automatically onto ACSs, a software design environment called CHAMPION was developed at the University of Tennessee. This environment permits high-level design entry using the Cantata graphical programming environment from KRI and hides from the user the low-level details of the Hardware architecture. Thus, ACSs can be utilized by a wider audience and application development can be accomplished in less time. Furthermore, CHAMPION provides the means to map onto multiple ACS platforms, thereby exploiting rapid advances being made in Hardware.
Amr Elchouemi - One of the best experts on this subject based on the ideXlab platform.
-
ICECS - Netlist partitioning method suitable for adaptive computing systems
2013 IEEE 20th International Conference on Electronics Circuits and Systems (ICECS), 2013Co-Authors: Nabil F. Kerkiz, Amr ElchouemiAbstract:Adaptive computing systems (ACSs) are flexible Hardware accelerators for applications in domains such as image and digital signal processing. However, the mapping of applications onto ACSs using the traditional methods can take long time for a Hardware Engineer to develop and debug. A software design environment called CHAMPION was developed at the University of Tennessee to enable the automated mapping of applications onto ACSs. In this paper the compilation path of CHAMPION is described and a new recursive partitioning method based on topological ordering and levelization (RPL) is presented. The proposed method performs multi-FPGA partitioning by taking into account six different partitioning constraints.
-
Netlist partitioning method suitable for adaptive computing systems
2013 IEEE 20th International Conference on Electronics Circuits and Systems (ICECS), 2013Co-Authors: Nabil F. Kerkiz, Amr ElchouemiAbstract:Adaptive computing systems (ACSs) are flexible Hardware accelerators for applications in domains such as image and digital signal processing. However, the mapping of applications onto ACSs using the traditional methods can take long time for a Hardware Engineer to develop and debug. A software design environment called CHAMPION was developed at the University of Tennessee to enable the automated mapping of applications onto ACSs. In this paper the compilation path of CHAMPION is described and a new recursive partitioning method based on topological ordering and levelization (RPL) is presented. The proposed method performs multi-FPGA partitioning by taking into account six different partitioning constraints.
Thad Welch - One of the best experts on this subject based on the ideXlab platform.
-
EvalWare: web resources and recommendations for DSP Hardware design [Best of The Web]
IEEE Signal Processing Magazine, 2009Co-Authors: Michael Morrow, Cameron Wright, Thad WelchAbstract:In this issue, "Best of the Web" focuses on web resources that are useful for understanding the features of digital signal processor (DSP) devices and using DSPs to build systems and applications. Most readers of this magazine are well versed in the theory and algorithms of digital signal processing. However, making the transition from DSP theory to DSP Hardware can be quite a challenge, especially for people whose computer Engineering background is not particularly extensive. The saying "the devil is in the details" was probably coined by a DSP Hardware Engineer! For example, an algorithm that performs beautifully in MATLAB can, when implemented in DSP Hardware, fail to run or--worse yet--seem to run fine but provide incorrect output. There are many implementation paths for DSP Hardware, with many large differences and many more subtle nuances that are keys to a successful design. We hope the reader won't underestimate the pitfalls that can wreak havoc on a DSP Hardware project.
