The Experts below are selected from a list of 7869 Experts worldwide ranked by ideXlab platform
Hongil Yoon - One of the best experts on this subject based on the ideXlab platform.
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single error correction and double adjacent error correction code for simultaneous testing of data bit and check bit arrays in memories
IEEE Transactions on Device and Materials Reliability, 2014Co-Authors: Sanguhn Cha, Hongil YoonAbstract:In this paper, a new single-error-correction and double-adjacent-error-correction (SEC-DAEC) code is proposed for simultaneous testing of the most general memory fault models in both data bit and check bit arrays of memories. Simultaneous testing of data bit and check bit arrays eliminates the test time and Hardware Overheads required for separate check bit array tests. In order to test data bit and check bit arrays simultaneously, the proposed SEC-DAEC code generates the identical data background patterns for data bit and check bit arrays. The testable faults using the proposed SEC-DAEC code are the most general memory fault models such as single-cell faults and interword and intraword coupling faults. Simultaneous testing of data bit and check bit arrays using the proposed SEC-DAEC codes brings significant decreases of about 27.3%, 17.9%, and 11.1% in the time required for memory array tests for 16, 32, and 64 data bits per word, respectively. In addition, the number of ones in the H-matrix of the proposed SEC-DAEC code is brought close to the theoretical minimum number, thereby reducing the complexity of the check bit generator.
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single error correction code for simultaneous testing of data bit and check bit arrays for word oriented memories
IEEE Transactions on Device and Materials Reliability, 2013Co-Authors: Sanguhn Cha, Hongil YoonAbstract:A novel single-error-correction (SEC) code is proposed in order to test various fault models simultaneously in both data bit and check bit arrays for word-oriented memories (WOMs). Simultaneous testing of data bit and check bit arrays eliminates the test time and Hardware Overheads required for separate check bit array tests. The testable faults using the proposed SEC code are the most well-known memory fault models such as single-cell faults and interword and intraword coupling faults. The regularity in data backgrounds (DBs) corresponding to these fault models for WOM tests is investigated. Henceforth, the proposed SEC code is constructed to generate the identical DB patterns for data bit and check bit arrays. Simultaneous testing of data bit and check bit arrays using the proposed SEC codes brings a significant decrease of about 9.9%-33.3% in the time required for memory array tests for 8, 16, 32, and 64 data bits per word. In addition, the number of ones in the H-matrix of the proposed SEC code is brought close to the theoretical minimum number, thereby reducing the complexity of the check bit generator. For various applications, the proposed SEC code can be represented by many forms of H-matrices.
Sarita V Adve - One of the best experts on this subject based on the ideXlab platform.
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mswat low cost Hardware fault detection and diagnosis for multicore systems
International Symposium on Microarchitecture, 2009Co-Authors: Siva Kumar Sastry Hari, Pradeep Ramachandran, Byn Choi, Sarita V AdveAbstract:Continued technology scaling is resulting in systems with billions of devices. Unfortunately, these devices are prone to failures from various sources, resulting in even commodity systems being affected by the growing reliability threat. Thus, traditional solutions involving high redundancy or piecemeal solutions targeting specific failure modes will no longer be viable owing to their high Overheads. Recent reliability solutions have explored using low-cost monitors that watch for anomalous software behavior as a symptom of Hardware faults. We previously proposed the SWAT system that uses such low-cost detectors to detect Hardware faults, and a higher cost mechanism for diagnosis. However, all of the prior work in this context, including SWAT, assumes single-threaded applications and has not been demonstrated for multithreaded applications running on multicore systems. This paper presents mSWAT, the first work to apply symptom based detection and diagnosis for faults in multicore architectures running multithreaded software. For detection, we extend the symptom-based detectors in SWAT and show that they result in a very low Silent Data Corruption (SDC) rate for both permanent and transient Hardware faults. For diagnosis, the multicore environment poses significant new challenges. First, deterministic replay required for SWAT's single-threaded diagnosis incurs higher Overheads for multithreaded workloads. Second, the fault may propagate to fault-free cores resulting in symptoms from fault-free cores and no available known-good core, breaking fundamental assumptions of SWAT's diagnosis algorithm. We propose a novel permanent fault diagnosis algorithm for multithreaded applications running on multicore systems that uses a lightweight isolated deterministic replay to diagnose the faulty core with no prior knowledge of a known good core. Our results show that this technique successfully diagnoses over 95% of the detected permanent faults while incurring low Hardware Overheads. mSWAT thus offers an affordable solution to protect future multicore systems from Hardware faults.
Sanguhn Cha - One of the best experts on this subject based on the ideXlab platform.
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single error correction and double adjacent error correction code for simultaneous testing of data bit and check bit arrays in memories
IEEE Transactions on Device and Materials Reliability, 2014Co-Authors: Sanguhn Cha, Hongil YoonAbstract:In this paper, a new single-error-correction and double-adjacent-error-correction (SEC-DAEC) code is proposed for simultaneous testing of the most general memory fault models in both data bit and check bit arrays of memories. Simultaneous testing of data bit and check bit arrays eliminates the test time and Hardware Overheads required for separate check bit array tests. In order to test data bit and check bit arrays simultaneously, the proposed SEC-DAEC code generates the identical data background patterns for data bit and check bit arrays. The testable faults using the proposed SEC-DAEC code are the most general memory fault models such as single-cell faults and interword and intraword coupling faults. Simultaneous testing of data bit and check bit arrays using the proposed SEC-DAEC codes brings significant decreases of about 27.3%, 17.9%, and 11.1% in the time required for memory array tests for 16, 32, and 64 data bits per word, respectively. In addition, the number of ones in the H-matrix of the proposed SEC-DAEC code is brought close to the theoretical minimum number, thereby reducing the complexity of the check bit generator.
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single error correction code for simultaneous testing of data bit and check bit arrays for word oriented memories
IEEE Transactions on Device and Materials Reliability, 2013Co-Authors: Sanguhn Cha, Hongil YoonAbstract:A novel single-error-correction (SEC) code is proposed in order to test various fault models simultaneously in both data bit and check bit arrays for word-oriented memories (WOMs). Simultaneous testing of data bit and check bit arrays eliminates the test time and Hardware Overheads required for separate check bit array tests. The testable faults using the proposed SEC code are the most well-known memory fault models such as single-cell faults and interword and intraword coupling faults. The regularity in data backgrounds (DBs) corresponding to these fault models for WOM tests is investigated. Henceforth, the proposed SEC code is constructed to generate the identical DB patterns for data bit and check bit arrays. Simultaneous testing of data bit and check bit arrays using the proposed SEC codes brings a significant decrease of about 9.9%-33.3% in the time required for memory array tests for 8, 16, 32, and 64 data bits per word. In addition, the number of ones in the H-matrix of the proposed SEC code is brought close to the theoretical minimum number, thereby reducing the complexity of the check bit generator. For various applications, the proposed SEC code can be represented by many forms of H-matrices.
Jean-philippe Diguet - One of the best experts on this subject based on the ideXlab platform.
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A Code Compression Method to Cope with Security Hardware Overheads
19th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'07), 2007Co-Authors: Eduardo Wanderley, Romain Vaslin, Guy Gogniat, Jean-philippe DiguetAbstract:Code Compression has been used to alleviate the memory requirements as well as to improve performance and/or minimize energy consumption. On the other hand, implementing security primitives on Embedded Systems is always costly in terms of area and performance. In this paper we present a code compression method, the IBC-EI (instruction based compression with encryption and integrity checking), tailored to provide integrity checking and encryption to secure processor-memory transactions. The principle is to keep the code compressed and ciphered in the memory, thus reducing the memory footprint and providing more information per memory access. For the Leon processor and a set of benchmarks from the Mediabench and MiBench suites the habitual Overheads due to security trend to zero in comparison to a system without security neither compression.
Siva Kumar Sastry Hari - One of the best experts on this subject based on the ideXlab platform.
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mswat low cost Hardware fault detection and diagnosis for multicore systems
International Symposium on Microarchitecture, 2009Co-Authors: Siva Kumar Sastry Hari, Pradeep Ramachandran, Byn Choi, Sarita V AdveAbstract:Continued technology scaling is resulting in systems with billions of devices. Unfortunately, these devices are prone to failures from various sources, resulting in even commodity systems being affected by the growing reliability threat. Thus, traditional solutions involving high redundancy or piecemeal solutions targeting specific failure modes will no longer be viable owing to their high Overheads. Recent reliability solutions have explored using low-cost monitors that watch for anomalous software behavior as a symptom of Hardware faults. We previously proposed the SWAT system that uses such low-cost detectors to detect Hardware faults, and a higher cost mechanism for diagnosis. However, all of the prior work in this context, including SWAT, assumes single-threaded applications and has not been demonstrated for multithreaded applications running on multicore systems. This paper presents mSWAT, the first work to apply symptom based detection and diagnosis for faults in multicore architectures running multithreaded software. For detection, we extend the symptom-based detectors in SWAT and show that they result in a very low Silent Data Corruption (SDC) rate for both permanent and transient Hardware faults. For diagnosis, the multicore environment poses significant new challenges. First, deterministic replay required for SWAT's single-threaded diagnosis incurs higher Overheads for multithreaded workloads. Second, the fault may propagate to fault-free cores resulting in symptoms from fault-free cores and no available known-good core, breaking fundamental assumptions of SWAT's diagnosis algorithm. We propose a novel permanent fault diagnosis algorithm for multithreaded applications running on multicore systems that uses a lightweight isolated deterministic replay to diagnose the faulty core with no prior knowledge of a known good core. Our results show that this technique successfully diagnoses over 95% of the detected permanent faults while incurring low Hardware Overheads. mSWAT thus offers an affordable solution to protect future multicore systems from Hardware faults.
