The Experts below are selected from a list of 34707 Experts worldwide ranked by ideXlab platform
H Philip S Wong - One of the best experts on this subject based on the ideXlab platform.
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a compact model for metal oxide resistive random access Memory with experiment verification
IEEE Transactions on Electron Devices, 2016Co-Authors: Zizhen Jiang, Lin Yang, Kay Song, Zia Karim, H Philip S WongAbstract:A dynamic Verilog-A resistive random access Memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-Memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the Memory Array.
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capacity optimization of emerging Memory systems a shannon inspired approach to device characterization
International Electron Devices Meeting, 2014Co-Authors: Jesse Engel, Burc S Eryilmaz, Sangbum Kim, M Brightsky, Chung H Lam, Hsianglan Lung, Bruno A Olshausen, H Philip S WongAbstract:Traditional approaches to Memory characterize the number of distinct states achievable at a given Raw Bit Error Rate (RBER). Using Phase Change Memory (PCM) as an example analog-valued Memory, we demonstrate that measuring the mutual information allows optimal design of read-write circuits to increase data storage capacity by 30%. Further, we show the framework can be used for energy efficient Memory design by optimizing simulations of a 1Mb Memory Array to consume 32% less energy/bit. This work provides an information-theoretic framework to guide the design and characterization of other analog-valued emerging Memory such as RRAM and CBRAM.
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effect of wordline bitline scaling on the performance energy consumption and reliability of cross point Memory Array
ACM Journal on Emerging Technologies in Computing Systems, 2013Co-Authors: Jiale Liang, Stanley Yeh, S. Simon Wong, H Philip S WongAbstract:The impact of wordline/bitline metal wire scaling on the write/read performance, energy consumption, speed, and reliability of the cross-point Memory Array is quantitatively studied for technology nodes down to single-digit nm. The impending resistivity increase in the Cu wires is found to cause significant decrease of both write and read window margins at the regime when electron surface scattering and grain boundary scattering are substantial. At deeply-scaled device dimensions, the wire energy dissipation and wire latency become comparable to or even exceed the intrinsic values of Memory cells. The large current density flowing through the wordlines/bitlines raises additional reliability concerns for the cross-point Memory Array. All these issues are exacerbated at smaller Memory resistance values and larger Memory Array sizes. They thereby impose strict constraints on the Memory device design and preclude the realization of large-scale cross-point Memory Array with minimum feature sizes beyond the 10 nm node. A rethink in the design methodology of cross-point Memory to incorporate and mitigate the scaling effects of wordline/bitline is necessary. Possible solutions include the use of Memory wires with better conductivity and scalability, Memory Arrays with smaller partition sizes, and Memory elements with larger resistance values and resistance ratios.
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cross point Memory Array without cell selectors device characteristics and data storage pattern dependencies
IEEE Transactions on Electron Devices, 2010Co-Authors: Jiale Liang, H Philip S WongAbstract:Cross-point Memory architecture offers high device density, yet it suffers from substantial sneak path leakages, which result in large power dissipation and a small sensing margin. The parasitic resistance associated with the interconnects further degrades the output signal and imposes an additional limitation on the maximum allowable Array size. In this paper, we study the device requirements of a resistive cross-point Memory Array under the worst-case write and read operations. We focus on the data pattern dependence of the Memory Array and compare the effect of the Memory cell resistance values and resistance ratio for determining the maximum Array size. The number of cells in the Array can reach 106 with a signal swing > 50% of the reading voltage when Ron is beyond 3 M and Roff/Ron is greater than 2. A large Memory cell resistance value can further reduce the power consumption, obviate the need for a large Roff/Ron ratio, and avoid the inclusion of cell selection devices. The effect of the nonlinearity of the I -V characteristics of the Memory cells is also investigated. The nonlinearity calls for a substantial tradeoff between the Memory cell resistance values and the resistance ratio, and must be taken into consideration for the device design.
Xiao Yan Liu - One of the best experts on this subject based on the ideXlab platform.
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stateful logic operations in one transistor one resistor resistive random access Memory Array
IEEE Electron Device Letters, 2019Co-Authors: Wensheng Shen, Lifeng Liu, Peng Huang, Bin Gao, Zheng Zhou, Xiao Yan Liu, He Qian, Mengqi Fan, Runze Han, Xing ZhangAbstract:Nonvolatile and cascadable stateful logic operations are experimentally demonstrated within a 1 k-bit one-transistor-one-resistor (1T1R) resistive random access Memory (RRAM) Array, where NAND gates serve as the building blocks. A robust dual-gate-voltage operation scheme is proposed. The effects of the transistor ON logic operation and the robustness to device parameter variations are discussed. The parallel 4-bit bitwise XOR operation is experimentally implemented in the 1T1R Array by cascading NAND gates. This letter presents a feasible approach to in-Memory computing for large-scale circuits.
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disturbance characteristics of half selected cells in a cross point resistive switching Memory Array
Nanotechnology, 2016Co-Authors: Zhe Chen, Lifeng Liu, Hong Yu Chen, Peng Huang, Bin Gao, Bing Chen, Zizhen Jiang, Rui Liu, Feifei Zhang, Xiao Yan LiuAbstract:Disturbance characteristics of cross-point resistive random access Memory (RRAM) Arrays are comprehensively studied in this paper. An analytical model is developed to quantify the number of pulses (#Pulse) the cell can bear before disturbance occurs under various sub-switching voltage stresses based on physical understanding. An evaluation methodology is proposed to assess the disturb behavior of half-selected (HS) cells in cross-point RRAM Arrays by combining the analytical model and SPICE simulation. The characteristics of cross-point RRAM Arrays such as energy consumption, reliable operating cycles and total error bits are evaluated by the methodology. A possible solution to mitigate disturbance is proposed.
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A SPICE model of resistive random access Memory for large-scale Memory Array simulation
IEEE Electron Device Letters, 2014Co-Authors: Haitong Li, Peng Huang, Bin Gao, Xiao Yan Liu, Bing Chen, Jinfeng KangAbstract:A SPICE model of oxide-based resistive random access Memory (RRAM) for dc and transient behaviors is developed based on the conductive filament evolution model and is implemented in large-scale Array simulation. The simulations of one transistor-one resistor RRAM Array up to 16 kb with wire resistance (Rwire) and capacitance (Cwire) indicate that: 1) resistance-capacitance delay during RESET and leakage current during SET have significant impact on write operations; 2) with Array size enlarging, the power dissipation increases during RESET but decreases during SET; and 3) the increased Rwire and Cwire lead to the degradation of high resistance state and the fluctuation of low resistance state, respectively.
Bin Gao - One of the best experts on this subject based on the ideXlab platform.
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stateful logic operations in one transistor one resistor resistive random access Memory Array
IEEE Electron Device Letters, 2019Co-Authors: Wensheng Shen, Lifeng Liu, Peng Huang, Bin Gao, Zheng Zhou, Xiao Yan Liu, He Qian, Mengqi Fan, Runze Han, Xing ZhangAbstract:Nonvolatile and cascadable stateful logic operations are experimentally demonstrated within a 1 k-bit one-transistor-one-resistor (1T1R) resistive random access Memory (RRAM) Array, where NAND gates serve as the building blocks. A robust dual-gate-voltage operation scheme is proposed. The effects of the transistor ON logic operation and the robustness to device parameter variations are discussed. The parallel 4-bit bitwise XOR operation is experimentally implemented in the 1T1R Array by cascading NAND gates. This letter presents a feasible approach to in-Memory computing for large-scale circuits.
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thermal stability of hfo x based resistive Memory Array a temperature coefficient study
IEEE Electron Device Letters, 2018Co-Authors: Xiaohu Wang, Bin Gao, Ning Deng, He QianAbstract:In HfOx-based RRAM Array, the temperature dependent shift of resistance at the low resistance state is statistically distributed. The differences in temperature dependent shifts among cells bring challenge to the reliability of analog or multilevel resistive switching behavior, namely thermal instability, which is characterized by the temperature coefficient ( $\text{T}_{\alpha }$ ) of RRAM. Its effect on RRAM performances was studied by pulse programming and retention measurement. Through atomistic simulation, this letter showed that thermal instability of cells with a positive $\text{T}_{\alpha }$ was related to the arrangement of oxygen vacancy inside the switching layer. Based on this model, the probability of cells with a positive $\text{T}_{\alpha }$ was found to be effectively reduced by introducing a baking process which led to an overall improvement of retention for the 1 k bit Array.
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disturbance characteristics of half selected cells in a cross point resistive switching Memory Array
Nanotechnology, 2016Co-Authors: Zhe Chen, Lifeng Liu, Hong Yu Chen, Peng Huang, Bin Gao, Bing Chen, Zizhen Jiang, Rui Liu, Feifei Zhang, Xiao Yan LiuAbstract:Disturbance characteristics of cross-point resistive random access Memory (RRAM) Arrays are comprehensively studied in this paper. An analytical model is developed to quantify the number of pulses (#Pulse) the cell can bear before disturbance occurs under various sub-switching voltage stresses based on physical understanding. An evaluation methodology is proposed to assess the disturb behavior of half-selected (HS) cells in cross-point RRAM Arrays by combining the analytical model and SPICE simulation. The characteristics of cross-point RRAM Arrays such as energy consumption, reliable operating cycles and total error bits are evaluated by the methodology. A possible solution to mitigate disturbance is proposed.
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Optimized learning scheme for grayscale image recognition in a RRAM based analog neuromorphic system
2015 IEEE International Electron Devices Meeting (IEDM), 2015Co-Authors: Zhe Chen, Xijia Liu, Dongbin Zhu, Lifeng Liu, Wenjia Ma, Haitong Li, Jinfeng Kang, Peng Huang, Bin Gao, Zheng Zhou, Hong Yu ChenAbstract:An analog neuromorphic system is developed based on the fabricated resistive switching Memory Array. A novel training scheme is proposed to optimize the performance of the analog system by utilizing the segmented synaptic behavior. The scheme is demonstrated on a grayscale image recognition. According to the experiment results, the optimized one improves learning accuracy from 77.83% to 91.32%, decreases energy consumption by more than two orders, and substantially boosts learning efficiency compared to the traditional training scheme.
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A SPICE model of resistive random access Memory for large-scale Memory Array simulation
IEEE Electron Device Letters, 2014Co-Authors: Haitong Li, Peng Huang, Bin Gao, Xiao Yan Liu, Bing Chen, Jinfeng KangAbstract:A SPICE model of oxide-based resistive random access Memory (RRAM) for dc and transient behaviors is developed based on the conductive filament evolution model and is implemented in large-scale Array simulation. The simulations of one transistor-one resistor RRAM Array up to 16 kb with wire resistance (Rwire) and capacitance (Cwire) indicate that: 1) resistance-capacitance delay during RESET and leakage current during SET have significant impact on write operations; 2) with Array size enlarging, the power dissipation increases during RESET but decreases during SET; and 3) the increased Rwire and Cwire lead to the degradation of high resistance state and the fluctuation of low resistance state, respectively.
H.-j. S H.s. Kim - One of the best experts on this subject based on the ideXlab platform.
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Multi-layer cross-point binary oxide resistive Memory (OxRRAM) for post-NAND storage application
IEEE InternationalElectron Devices Meeting 2005. IEDM Technical Digest., 2005Co-Authors: In Gyu Baek, D.c. C Kim, H.-j. S H.s. Kim, E.k. K Yim, J.e. E J.h. H Lee, S.e. E Ahn, M. S. Lee, B.i. Ryu, Y.k. Cha, S Seo, S. O. Park, M.j. Lee, J C Park, H.s. KimAbstract:Feasibility of the multi-layer cross-point structured binary oxide resistive Memory (OxRRAM) has been tested for next generation non-volatile random access high density data storage application. Novel plug contact type bottom electrode (plug-BE) could reduce active Memory cell diameter down to 50nm with smaller operation current and improved switching distributions. With 2 additional masks, one layer of plug-BE included cross-point Memory Array could be added on top of another one. No signal of inter-layer interference has been observed. Also, prototype binary oxide based diodes have been fabricated for the purpose of suppressing intra-layer interference of cross-point Memory Array
Peng Huang - One of the best experts on this subject based on the ideXlab platform.
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stateful logic operations in one transistor one resistor resistive random access Memory Array
IEEE Electron Device Letters, 2019Co-Authors: Wensheng Shen, Lifeng Liu, Peng Huang, Bin Gao, Zheng Zhou, Xiao Yan Liu, He Qian, Mengqi Fan, Runze Han, Xing ZhangAbstract:Nonvolatile and cascadable stateful logic operations are experimentally demonstrated within a 1 k-bit one-transistor-one-resistor (1T1R) resistive random access Memory (RRAM) Array, where NAND gates serve as the building blocks. A robust dual-gate-voltage operation scheme is proposed. The effects of the transistor ON logic operation and the robustness to device parameter variations are discussed. The parallel 4-bit bitwise XOR operation is experimentally implemented in the 1T1R Array by cascading NAND gates. This letter presents a feasible approach to in-Memory computing for large-scale circuits.
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disturbance characteristics of half selected cells in a cross point resistive switching Memory Array
Nanotechnology, 2016Co-Authors: Zhe Chen, Lifeng Liu, Hong Yu Chen, Peng Huang, Bin Gao, Bing Chen, Zizhen Jiang, Rui Liu, Feifei Zhang, Xiao Yan LiuAbstract:Disturbance characteristics of cross-point resistive random access Memory (RRAM) Arrays are comprehensively studied in this paper. An analytical model is developed to quantify the number of pulses (#Pulse) the cell can bear before disturbance occurs under various sub-switching voltage stresses based on physical understanding. An evaluation methodology is proposed to assess the disturb behavior of half-selected (HS) cells in cross-point RRAM Arrays by combining the analytical model and SPICE simulation. The characteristics of cross-point RRAM Arrays such as energy consumption, reliable operating cycles and total error bits are evaluated by the methodology. A possible solution to mitigate disturbance is proposed.
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Optimized learning scheme for grayscale image recognition in a RRAM based analog neuromorphic system
2015 IEEE International Electron Devices Meeting (IEDM), 2015Co-Authors: Zhe Chen, Xijia Liu, Dongbin Zhu, Lifeng Liu, Wenjia Ma, Haitong Li, Jinfeng Kang, Peng Huang, Bin Gao, Zheng Zhou, Hong Yu ChenAbstract:An analog neuromorphic system is developed based on the fabricated resistive switching Memory Array. A novel training scheme is proposed to optimize the performance of the analog system by utilizing the segmented synaptic behavior. The scheme is demonstrated on a grayscale image recognition. According to the experiment results, the optimized one improves learning accuracy from 77.83% to 91.32%, decreases energy consumption by more than two orders, and substantially boosts learning efficiency compared to the traditional training scheme.
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A SPICE model of resistive random access Memory for large-scale Memory Array simulation
IEEE Electron Device Letters, 2014Co-Authors: Haitong Li, Peng Huang, Bin Gao, Xiao Yan Liu, Bing Chen, Jinfeng KangAbstract:A SPICE model of oxide-based resistive random access Memory (RRAM) for dc and transient behaviors is developed based on the conductive filament evolution model and is implemented in large-scale Array simulation. The simulations of one transistor-one resistor RRAM Array up to 16 kb with wire resistance (Rwire) and capacitance (Cwire) indicate that: 1) resistance-capacitance delay during RESET and leakage current during SET have significant impact on write operations; 2) with Array size enlarging, the power dissipation increases during RESET but decreases during SET; and 3) the increased Rwire and Cwire lead to the degradation of high resistance state and the fluctuation of low resistance state, respectively.
