The Experts below are selected from a list of 315 Experts worldwide ranked by ideXlab platform
M. Murakami - One of the best experts on this subject based on the ideXlab platform.
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SMC - Task-based dynamic fault tolerance and its safety considerations in humanoid robot applications
2007 IEEE International Conference on Systems Man and Cybernetics, 2007Co-Authors: M. MurakamiAbstract:Although the performance of humanoid robots is rapidly improving, very few dependability schemes suitable for humanoid robots have been presented thus far. In the future, various tasks ranging from daily chores to safety-related tasks will be carried out by individual humanoid robots. If the characteristics and importance of the tasks are different, the required fault-tolerant capabilities will also vary accordingly. Therefore, for mobile humanoid robots operating under power constraints, it is desirable to develop a dynamic fault tolerance capable of reducing power consumption because fault-tolerant designs involving Hardware Redundancy are power intensive. This paper proposes a task-based dynamic fault tolerance scheme based on the Hardware Redundancy of the computer unit, and describes the implementation of the proposed scheme by considering the safety in humanoid robot applications.
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SMC - Task-based Dynamic Fault Tolerance for Humanoid Robots
2006 IEEE International Conference on Systems Man and Cybernetics, 2006Co-Authors: M. MurakamiAbstract:Although the performance of humanoid robots is rapidly improving, very few dependability schemes suitable for humanoid robots have been presented thus far. In particular, the fault tolerance of the engine (i.e., CPU module) has not been discussed. In the future, various tasks ranging from daily chores to safety-related tasks will be carried out by individual humanoid robots. If the characteristics and importance of the given tasks are different, the required fault-tolerant capabilities will also vary accordingly. Therefore, for mobile humanoid robots operating under power constraints, a dynamic fault tolerance capable of reducing the power consumption is desirable because fault-tolerant designs involving Hardware Redundancy are power intensive. In addition, an appropriate safety operation must be determined for each task. This paper discusses the dependability of humanoid robots and proposes a task-based dynamic fault tolerance scheme as a vital concept for humanoid robot applications; this scheme is based on Hardware Redundancy of the engine.
Emna Amouri - One of the best experts on this subject based on the ideXlab platform.
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Impact of defect tolerance techniques on the criticality of a SRAM-based Mesh of Cluster FPGA
2014Co-Authors: Adrien Blanchardon, Roselyne Chotin-avot, Habib Mehrez, Emna AmouriAbstract:As device sizes shrink, circuits are increasingly prone to manufacturing defects. One of the future challenges is to find a way to use a maximum of defected manufactured circuits. One possible approach to this growing problem is to add Redundancy to propose defect-tolerant architectures. But, Hardware Redundancy increases area. In this paper, we propose a method to determine the most critical elements in a SRAM-based Mesh of Clusters FPGA and different strategies to locally insert Hardware Redundancy. Depending on the criticality, using defect tolerance, area and timing metrics, five different strategies are evaluated on the Mesh of Clusters architecture. We show that using these techniques on a Mesh of Clusters architecture permits to tolerate 4 times more defects than classic Hardware Redundancy techniques applied on industrial mesh FPGA. With local strategies, we obtain a best trade off between the number of defects bypassed (37.95%), the FPGA area overhead (21.84%) and the critical path delay increase (9.65%).
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Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using Hardware Redundancy
2014Co-Authors: Adrien Blanchardon, Roselyne Chotin-avot, Habib Mehrez, Emna AmouriAbstract:The technological evolution involves a higher number of physical defects in circuits after manufacturing. One of the future challenge is to find a way to use a maximum of defected manufactured circuits. In this paper, multiple techniques are proposed to avoid defects in the cluster local interconnect of a SRAM-based Mesh of Clusters FPGA. Using defect tolerance, area and timing metrics, two previous Hardware Redundancy strategies are evaluated on the Mesh of Clusters architecture : Fine Grain Redundancy (FGR) and Improved Fine Grain Redundancy (IFGR). We show that using these techniques on a cluster of a Mesh of Clusters architecture permits to tolerate 8 times more defects than on an industrial Mesh FPGA with a low area overhead (-6% for FGR and 22% for IFGR) and a low increase of Critical Path Delay (CPD)(6% for FGR and 2% for IFGR). We also proposed three new Redundancy strategies using spare resources : Distributed Feedbacks (DF) for crossbar down, Adapted Fine Grain Redundancy (AFGR) to avoid defective multiplexers and Upward Redundant Multiplexer (URM) for the crossbar up. Compared to the Mesh of Clusters architecture without defect tolerance techniques, the best trade off between defect tolerance (36.4%), area overhead (11.56%) and CPD (+7.46%) is obtained using AFGR. Using the other methods permits to considerably limit the area overhead (10.4% with URM) with a lesser number of defective elements bypassed (18% max).
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FPL - Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using Hardware Redundancy
2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014Co-Authors: Adrien Blanchardon, Roselyne Chotin-avot, Habib Mehrez, Emna AmouriAbstract:The technological evolution involves a higher number of physical defects in circuits after manufacturing. One of the future challenge is to find a way to use a maximum of defected manufactured circuits. In this paper, multiple techniques are proposed to avoid defects in the cluster local interconnect of a SRAM-based Mesh of Clusters FPGA. Using defect tolerance, area and timing metrics, two previous Hardware Redundancy strategies are evaluated on the Mesh of Clusters architecture : Fine Grain Redundancy (FGR) and Improved Fine Grain Redundancy (IFGR). We show that using these techniques on a cluster of a Mesh of Clusters architecture permits to tolerate 8 times more defects than on an industrial Mesh FPGA with a low area overhead (−6% for FGR and 22% for IFGR) and a low increase of Critical Path Delay (CPD)(6% for FGR and 2% for IFGR). We also proposed three new Redundancy strategies using spare resources : Distributed Feedbacks (DF) for crossbar down, Adapted Fine Grain Redundancy (AFGR) to avoid defective multiplexers and Upward Redundant Multiplexer (URM) for the crossbar up. Compared to the Mesh of Clusters architecture without defect tolerance techniques, the best trade off between defect tolerance (36.4%), area overhead (11.56%) and CPD (+7.46%) is obtained using AFGR. Using the other methods permits to considerably limit the area overhead (10.4% with URM) with a lesser number of defective elements bypassed (18% max).
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ReConFig - Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA
2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14), 2014Co-Authors: Adrien Blanchardon, Roselyne Chotin-avot, Habib Mehrez, Emna AmouriAbstract:As device sizes shrink, circuits are increasingly prone to manufacturing defects. One of the future challenges is to find a way to use a maximum of defected manufactured circuits. One possible approach to this growing problem is to add Redundancy to propose defect-tolerant architectures. But, Hardware Redundancy increases area. In this paper, we propose a method to determine the most critical elements in a SRAM-based Mesh of Clusters FPGA and different strategies to locally insert Hardware Redundancy. Depending on the criticality, using defect tolerance, area and timing metrics, five different strategies are evaluated on the Mesh of Clusters architecture. We show that using these techniques on a Mesh of Clusters architecture permits to tolerate 4 times more defects than classic Hardware Redundancy techniques applied on industrial mesh FPGA. With local strategies, we obtain a best trade off between the number of defects bypassed (37.95%), the FPGA area overhead (21.84%) and the critical path delay increase (9.65%).
Ramesh Karri - One of the best experts on this subject based on the ideXlab platform.
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Fault secure datapath synthesis using hybrid time and Hardware Redundancy
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004Co-Authors: Kaijie Wu, Ramesh KarriAbstract:A fault-secure datapath either generates a correct result or signals an error. This paper presents a register transfer level concurrent error detection (CED) technique that uses hybrid time and Hardware Redundancy to optimize the time and area overhead associated with fault security. The proposed technique combines the idle computation cycles in a datapath with selective breaking of data dependences of the normal computation. Designers can tradeoff time and Hardware overhead by varying these design parameters. We present an algorithm to synthesize fault secure designs and validate it using Synopsys' behavioral compiler.
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ITC - Register transfer level approach to hybrid time and Hardware Redundancy based fault secure datapath synthesis
International Test Conference 2003. Proceedings. ITC 2003., 2003Co-Authors: Kaijie Wu, Ramesh KarriAbstract:A fault-secure datapath either generates a correct result or signals an error. This paper presents a register transfer level Concurrent Error Detection (CEO) technique that uses hybrid time and Hardware Redundancy to optimize the time and area overhead associated with fault security. The proposed technique combines the idle computation cycles in a datapath with selective breaking of data dependences of the normal computation. Designers can trade-off time and Hardware overhead by varying these design parameters. We present an algorithm to synthesize fault secure designs and validate it using Synopsys Behavioral Compiler.
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register transfer level approach to hybrid time and Hardware Redundancy based fault secure datapath synthesis
International Test Conference, 2003Co-Authors: Ramesh KarriAbstract:A fault-secure datapath either generates a correct result or signals an error. This paper presents a register transfer level Concurrent Error Detection (CEO) technique that uses hybrid time and Hardware Redundancy to optimize the time and area overhead associated with fault security. The proposed technique combines the idle computation cycles in a datapath with selective breaking of data dependences of the normal computation. Designers can trade-off time and Hardware overhead by varying these design parameters. We present an algorithm to synthesize fault secure designs and validate it using Synopsys Behavioral Compiler.
Kevin Skadron - One of the best experts on this subject based on the ideXlab platform.
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a Hardware Redundancy and recovery mechanism for reliable scientific computation on graphics processors
International Conference on Computer Graphics and Interactive Techniques, 2007Co-Authors: Jeremy W Sheaffer, David Luebke, Kevin SkadronAbstract:General purpose computation on graphics processors (GPGPU) has rapidly evolved since the introduction of commodity programmable graphics Hardware. With the appearance of GPGPU computation-oriented APIs such as AMD's Close to the Metal (CTM) and NVIDIA's Compute Unified Device Architecture (CUDA), we begin to see GPU vendors putting financial stakes into this non-graphics, one-time niche market. Major supercomputing installations are building GPGPU clusters to take advantage of massively parallel floating point capabilities, and Folding@Home has even released a GPU port of its protein folding distributed computation client. But in order for GPGPU to truly become important to the supercomputing community, vendors will have to address the heretofore unimportant reliability concerns of graphics processors. We present a Hardware Redundancy-based approach to reliability for general purpose computation on GPUs that requires minimal change to existing GPU architectures. Upon detecting an error, the system invokes an automatic recovery mechanism that only recomputes erroneous results. Our results show that our technique imposes less than a 1.5 x performance penalty and saves energy for GPGPU but is completely transparent to general graphics and does not affect the performance of the games that drive the market.
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Graphics Hardware - A Hardware Redundancy and recovery mechanism for reliable scientific computation on graphics processors
2007Co-Authors: Jeremy W Sheaffer, David Luebke, Kevin SkadronAbstract:General purpose computation on graphics processors (GPGPU) has rapidly evolved since the introduction of commodity programmable graphics Hardware. With the appearance of GPGPU computation-oriented APIs such as AMD's Close to the Metal (CTM) and NVIDIA's Compute Unified Device Architecture (CUDA), we begin to see GPU vendors putting financial stakes into this non-graphics, one-time niche market. Major supercomputing installations are building GPGPU clusters to take advantage of massively parallel floating point capabilities, and Folding@Home has even released a GPU port of its protein folding distributed computation client. But in order for GPGPU to truly become important to the supercomputing community, vendors will have to address the heretofore unimportant reliability concerns of graphics processors. We present a Hardware Redundancy-based approach to reliability for general purpose computation on GPUs that requires minimal change to existing GPU architectures. Upon detecting an error, the system invokes an automatic recovery mechanism that only recomputes erroneous results. Our results show that our technique imposes less than a 1.5 x performance penalty and saves energy for GPGPU but is completely transparent to general graphics and does not affect the performance of the games that drive the market.
Adrien Blanchardon - One of the best experts on this subject based on the ideXlab platform.
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Impact of defect tolerance techniques on the criticality of a SRAM-based Mesh of Cluster FPGA
2014Co-Authors: Adrien Blanchardon, Roselyne Chotin-avot, Habib Mehrez, Emna AmouriAbstract:As device sizes shrink, circuits are increasingly prone to manufacturing defects. One of the future challenges is to find a way to use a maximum of defected manufactured circuits. One possible approach to this growing problem is to add Redundancy to propose defect-tolerant architectures. But, Hardware Redundancy increases area. In this paper, we propose a method to determine the most critical elements in a SRAM-based Mesh of Clusters FPGA and different strategies to locally insert Hardware Redundancy. Depending on the criticality, using defect tolerance, area and timing metrics, five different strategies are evaluated on the Mesh of Clusters architecture. We show that using these techniques on a Mesh of Clusters architecture permits to tolerate 4 times more defects than classic Hardware Redundancy techniques applied on industrial mesh FPGA. With local strategies, we obtain a best trade off between the number of defects bypassed (37.95%), the FPGA area overhead (21.84%) and the critical path delay increase (9.65%).
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Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using Hardware Redundancy
2014Co-Authors: Adrien Blanchardon, Roselyne Chotin-avot, Habib Mehrez, Emna AmouriAbstract:The technological evolution involves a higher number of physical defects in circuits after manufacturing. One of the future challenge is to find a way to use a maximum of defected manufactured circuits. In this paper, multiple techniques are proposed to avoid defects in the cluster local interconnect of a SRAM-based Mesh of Clusters FPGA. Using defect tolerance, area and timing metrics, two previous Hardware Redundancy strategies are evaluated on the Mesh of Clusters architecture : Fine Grain Redundancy (FGR) and Improved Fine Grain Redundancy (IFGR). We show that using these techniques on a cluster of a Mesh of Clusters architecture permits to tolerate 8 times more defects than on an industrial Mesh FPGA with a low area overhead (-6% for FGR and 22% for IFGR) and a low increase of Critical Path Delay (CPD)(6% for FGR and 2% for IFGR). We also proposed three new Redundancy strategies using spare resources : Distributed Feedbacks (DF) for crossbar down, Adapted Fine Grain Redundancy (AFGR) to avoid defective multiplexers and Upward Redundant Multiplexer (URM) for the crossbar up. Compared to the Mesh of Clusters architecture without defect tolerance techniques, the best trade off between defect tolerance (36.4%), area overhead (11.56%) and CPD (+7.46%) is obtained using AFGR. Using the other methods permits to considerably limit the area overhead (10.4% with URM) with a lesser number of defective elements bypassed (18% max).
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FPL - Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using Hardware Redundancy
2014 24th International Conference on Field Programmable Logic and Applications (FPL), 2014Co-Authors: Adrien Blanchardon, Roselyne Chotin-avot, Habib Mehrez, Emna AmouriAbstract:The technological evolution involves a higher number of physical defects in circuits after manufacturing. One of the future challenge is to find a way to use a maximum of defected manufactured circuits. In this paper, multiple techniques are proposed to avoid defects in the cluster local interconnect of a SRAM-based Mesh of Clusters FPGA. Using defect tolerance, area and timing metrics, two previous Hardware Redundancy strategies are evaluated on the Mesh of Clusters architecture : Fine Grain Redundancy (FGR) and Improved Fine Grain Redundancy (IFGR). We show that using these techniques on a cluster of a Mesh of Clusters architecture permits to tolerate 8 times more defects than on an industrial Mesh FPGA with a low area overhead (−6% for FGR and 22% for IFGR) and a low increase of Critical Path Delay (CPD)(6% for FGR and 2% for IFGR). We also proposed three new Redundancy strategies using spare resources : Distributed Feedbacks (DF) for crossbar down, Adapted Fine Grain Redundancy (AFGR) to avoid defective multiplexers and Upward Redundant Multiplexer (URM) for the crossbar up. Compared to the Mesh of Clusters architecture without defect tolerance techniques, the best trade off between defect tolerance (36.4%), area overhead (11.56%) and CPD (+7.46%) is obtained using AFGR. Using the other methods permits to considerably limit the area overhead (10.4% with URM) with a lesser number of defective elements bypassed (18% max).
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ReConFig - Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA
2014 International Conference on ReConFigurable Computing and FPGAs (ReConFig14), 2014Co-Authors: Adrien Blanchardon, Roselyne Chotin-avot, Habib Mehrez, Emna AmouriAbstract:As device sizes shrink, circuits are increasingly prone to manufacturing defects. One of the future challenges is to find a way to use a maximum of defected manufactured circuits. One possible approach to this growing problem is to add Redundancy to propose defect-tolerant architectures. But, Hardware Redundancy increases area. In this paper, we propose a method to determine the most critical elements in a SRAM-based Mesh of Clusters FPGA and different strategies to locally insert Hardware Redundancy. Depending on the criticality, using defect tolerance, area and timing metrics, five different strategies are evaluated on the Mesh of Clusters architecture. We show that using these techniques on a Mesh of Clusters architecture permits to tolerate 4 times more defects than classic Hardware Redundancy techniques applied on industrial mesh FPGA. With local strategies, we obtain a best trade off between the number of defects bypassed (37.95%), the FPGA area overhead (21.84%) and the critical path delay increase (9.65%).
