The Experts below are selected from a list of 312 Experts worldwide ranked by ideXlab platform
Niraj K Jha - One of the best experts on this subject based on the ideXlab platform.
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variability tolerant Register Transfer level synthesis
International Conference on VLSI Design, 2008Co-Authors: Anish Muttreja, S Ravi, Niraj K JhaAbstract:Variability in circuit delay is a significant challenge in the design and synthesis of digital circuits. While the challenge is being addressed at various levels of the design hierarchy, we argue that modern Register-Transfer level (RTL) synthesis tools can be enhanced to deal with this problem in an alternate, yet effective, manner. Our solution involves the design of variability- tolerant, correct circuits assuming common-case, rather than worst-case, values for critical path delays. We propose a methodology to design variability-tolerant circuits that can, at runtime, detect and efficiently recover from delay errors, which would be inevitably introduced due to the use of common-case delay values. Variability-agnostic designs are automatically transformed into variability-tolerant circuits by the introduction of shadow logic to detect and recover from runtime errors, while exploiting data speculation to derive performance benefits. For various benchmark circuits, we show that the area overhead imposed by our scheme is only 11.4% on an average, while achieving upto 16.3% performance speedup over margined designs.
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VLSI Design - Variability-Tolerant Register-Transfer Level Synthesis
21st International Conference on VLSI Design (VLSID 2008), 2008Co-Authors: Anish Muttreja, S Ravi, Niraj K JhaAbstract:Variability in circuit delay is a significant challenge in the design and synthesis of digital circuits. While the challenge is being addressed at various levels of the design hierarchy, we argue that modern Register-Transfer level (RTL) synthesis tools can be enhanced to deal with this problem in an alternate, yet effective, manner. Our solution involves the design of variability- tolerant, correct circuits assuming common-case, rather than worst-case, values for critical path delays. We propose a methodology to design variability-tolerant circuits that can, at runtime, detect and efficiently recover from delay errors, which would be inevitably introduced due to the use of common-case delay values. Variability-agnostic designs are automatically transformed into variability-tolerant circuits by the introduction of shadow logic to detect and recover from runtime errors, while exploiting data speculation to derive performance benefits. For various benchmark circuits, we show that the area overhead imposed by our scheme is only 11.4% on an average, while achieving upto 16.3% performance speedup over margined designs.
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efficient design for testability solution based on unsatisfiability for Register Transfer level circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007Co-Authors: L Lingappan, Niraj K JhaAbstract:In this paper, we present a novel and accurate method for identifying design for testability (DFT) solutions for Register-Transfer level (RTL) circuits. Test generation proceeds by abstracting the circuit components using input/output propagation rules so that any justification/propagation event can be captured as a Boolean implication. Consequently, the RTL test generation problem is reduced to a satisfiability (SAT) instance. If a given SAT instance is not satisfiable, then we identify Boolean implications (also known as the unsatisfiable segment) that are responsible for unsatisfiability. We show that adding DFT elements is equivalent to modifying these clauses such that the unsatisfiable segment becomes satisfiable. The proposed DFT technique is both fast and accurate as it is applicable to RTL and mixed gate-level/RTL circuits and uses exact unsatisfiability conditions to identify the DFT solutions.
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tao regular expression based Register Transfer level testability analysis and optimization
IEEE Transactions on Very Large Scale Integration Systems, 2001Co-Authors: S Ravi, Ganesh Lakshminarayana, Niraj K JhaAbstract:In this paper, we present testability analysis and optimization (TAO), a novel methodology for Register-Transfer level (RTL) testability analysis and optimization of RTL controller/data path circuits. Unlike existing high-level testing techniques that cater restrictively to certain classes of circuits or design styles, TAO exploits the algebra of regular expressions to provide a unified framework for handling a wide variety of circuits including application-specific integrated circuits (ASICs), application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs), and microprocessors. We also augment TAO with a design-for-test (DFT) framework that can provide a low-cost testability solution by examining the tradeoffs in choosing from a diverse array of testability modifications like partial scan or test multiplexer insertion in different parts of the circuit. Test generation is symbolic and, hence, independent of bit width. Experimental results on benchmark circuits show that TAO is very efficient, in addition to being comprehensive. The fault coverage obtained is above 99% in all cases. The average area and delay overheads for incorporating testability into the benchmarks are only 3.2% and 1.0%, respectively. The test generation time is two-to-four orders of magnitude smaller than that associated with gate-level sequential test generators, while the test application times are comparable.
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a design for testability technique for Register Transfer level circuits using control data flow extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1998Co-Authors: Indradeep Ghosh, Anand Raghunathan, Niraj K JhaAbstract:In this paper, we present a technique for extracting functional (control/data flow) information from Register-Transfer level controller/data path circuits, and illustrate its use in design for hierarchical testability of these circuits. This scheme does not require any additional behavioral information. It identifies a suitable control and data flow from the Register-Transfer level circuit, and uses it to test each embedded element in the circuit by symbolically justifying its precomputed test set from the system primary inputs to the element inputs and symbolically propagating the output response to the system primary outputs. When symbolic justification and propagation become difficult, it inserts test multiplexers at suitable points to increase the symbolic controllability and observability of the circuit. These test multiplexers are mostly restricted to off-critical paths. Testability analysis and insertion are completely based on the Register-Transfer level circuit and the functional information automatically extracted from it, and are independent of the data path bit width owing to their symbolic nature. Furthermore, the data path test set is obtained as a byproduct of this analysis without any further search. Unlike many other design-for-testability techniques, this scheme makes the combined controller-data path very highly testable. It is general enough to handle control-flow-intensive Register-Transfer level circuits like protocol handlers as well as data-flow intensive circuits like digital filters. It results in low area/delay/power overheads, high fault coverage, and very low test generation times (because it is symbolic and independent of bit width). Also, a large part of our system-level test sets can be applied at speed. Experimental results on many benchmarks show the average area, delay, and power overheads for testability to be 3.1, 1.0, and 4.2%, respectively. Over 99% fault coverage is obtained in most cases with two-four orders of magnitude test generation time advantage over an efficient gate-level sequential test pattern generator and one-three orders of magnitude advantage over an efficient gate-level combinational test pattern generator (that assumes full scan). In addition, the test application times obtained for our method are comparable with those of gate-level sequential test pattern generators, and up to two orders of magnitude smaller than designs using full scan.
Ramesh Karri - One of the best experts on this subject based on the ideXlab platform.
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is Register Transfer level locking secure
Design Automation and Test in Europe, 2020Co-Authors: Chandan Karfa, Ramanuj Chouksey, Christian Pilato, Siddharth Garg, Ramesh KarriAbstract:Register Transfer Level (RTL) locking seeks to prevent intellectual property (IP) theft of a design by locking the RTL description that functions correctly on the application of a key. This paper evaluates the security of a state-of-the-art RTL locking scheme using a satisfiability modulo theories (SMT) based algorithm to retrieve the secret key. The attack first obtains the high-level behavior of the locked RTL, and then use an SMT based formulation to find so-called distinguishing input patterns (DIP)1. The attack methodology has two main advantages over the gate-level attacks. First, since the attack handles the design at the RTL, the method scales to large designs. Second, the attack does not apply separate unlocking strategies for the combinational and sequential parts of a design; it handles both styles via a unifying abstraction. We demonstrate the attack on locked RTL generated by TAO [1], a state-of-the-art RTL locking solution. Empirical results show that we can partially or completely break designs locked by TAO.
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DATE - Is Register Transfer level locking secure
2020 Design Automation & Test in Europe Conference & Exhibition (DATE), 2020Co-Authors: Chandan Karfa, Ramanuj Chouksey, Christian Pilato, Siddharth Garg, Ramesh KarriAbstract:Register Transfer Level (RTL) locking seeks to prevent intellectual property (IP) theft of a design by locking the RTL description that functions correctly on the application of a key. This paper evaluates the security of a state-of-the-art RTL locking scheme using a satisfiability modulo theories (SMT) based algorithm to retrieve the secret key. The attack first obtains the high-level behavior of the locked RTL, and then use an SMT based formulation to find so-called distinguishing input patterns (DIP)1. The attack methodology has two main advantages over the gate-level attacks. First, since the attack handles the design at the RTL, the method scales to large designs. Second, the attack does not apply separate unlocking strategies for the combinational and sequential parts of a design; it handles both styles via a unifying abstraction. We demonstrate the attack on locked RTL generated by TAO [1], a state-of-the-art RTL locking solution. Empirical results show that we can partially or completely break designs locked by TAO.
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Algorithm-level recomputing with shifted operands-a Register Transfer level concurrent error detection technique
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006Co-Authors: Ramesh KarriAbstract:This paper presents Algorithm-level REcomputing with Shifted Operands (ARESO), which is a new Register Transfer (RT) level time redundancy-based concurrent error detection (CED) technique. In REcomputing with Shifted Operands (RESO), operations (additions, subtractions, etc.) are carried out twice-once on the basic input and once on the shifted input. Results from these two operations are compared to detect an error. Although using RESO operators in RT-level designs is straightforward, it entails time and area overhead. In contrast, ARESO does not use specialized RESO operators. In ARESO, an algorithm is carried out twice-once on the basic input and once on the shifted input. Results from these two algorithm-level instantiations are compared to detect an error. By operating at the algorithm level, ARESO exploits RT-level scheduling, pipelining, operator chaining, and multicycling to incorporate user-specified error detection latencies. ARESO supports hardware versus performance versus error detection latency tradeoffs. The authors validated ARESO on practical design examples using the Synopsys Behavior Compiler (BC). An industry standard behavioral synthesis system.
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Algorithm level re-computing using implementation diversity: a Register Transfer level concurrent error detection technique
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2002Co-Authors: Ramesh KarriAbstract:Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time redundancy implemented can only detect transient faults. We present two algorithm-level time-redundancy-based CED schemes that exploit Register Transfer level (RTL) implementation diversity to detect transient and permanent faults. At the RTL, implementation diversity can be achieved either by changing the operation-to-operator allocation or by shifting the operands before re-computation. By exploiting allocation diversity and data diversity, a stuck-at fault will affect the two results in two different ways. The proposed schemes yield good fault detection probability with very low area overhead. We used the Synopsys behavior complier (BC), to validate the schemes.
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algorithm level re computing a Register Transfer level concurrent error detection technique
International Conference on Computer Aided Design, 2001Co-Authors: Ramesh KarriAbstract:In this paper we propose two algorithm-level time redundancy based Concurrent Error Detection (CED) schemes that exploit diversity in a Register Transfer (RT) level implementation. RT level diversity can be achieved either by changing the operation-to-operator allocation (allocation diversity) or by shifting the operands before re-computation (data diversity). By enabling a fault to affect the normal result and the re-computed result in two different ways, RT level diversity yields good CED capability with low area overhead. We used Synopsys Behavior Complier (BC) to implement the technique.
Fadi J. Kurdahi - One of the best experts on this subject based on the ideXlab platform.
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Register-Transfer Synthesis of Pipelined Data Paths
VLSI Design, 1994Co-Authors: Nohbyung Park, Fadi J. KurdahiAbstract:We present a new approach to the problem of Register-Transfer level design optimization of pipelined data paths. The output of high level synthesis procedures, such as Sehwa, consists of a schedule of operations into time steps, and a fixed set of hardware operators. In order to obtain a Register-Transfer level design, we must assign operations to specific operators, values to Registers, and finish the interconnections. We first perform module assignment with the goal of minimizing the interconnect requirements between RT-level components as a preprocessing procedure to the RT-level design. This will result in a smaller netlist which makes the design more compact and the design process more efficient. In addition to reducing the total number of interconnects, this approach will also reduce the total number of multiplexors in the design by eliminating unnecessary multiplexing at the inputs of shared modules. The interconnect sharing task is modeled as a constrained clique partitioning problem. We developed a fast and efficient polynomial time heuristic procedure to solve this problem. This procedure is 30–50 times faster than other existing heuristics while still producing better results for our purposes. Using this procedure, we can produce near optimal interconnect sharing schemes in a few seconds for most practical size pipelined designs. This efficient approach will enable designers to explore a larger portion of the design space and trade off various design parameters effectively.
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linking Register Transfer and physical levels of design
1993Co-Authors: Fadi J. Kurdahi, Daniel D. Gajski, C Ramachandran, V ChaiyakulAbstract:Author(s): Kurdahi, F J.; Gajski, D. D.; Ramachandran, C.; Chaiyakul, V. | Abstract: System and chip synthesis must evaluate candidate Register-Transfer (RT} architectures with respect to finished physical designs. Current RT level cost measures, however, are highly simplified and do not reflect the real physical design. Complete physical design, on the other hand, is quite costly, and infeasible to be iterated many times. In order to establish a more realistic assessment of layout effects, we proposed a new layout model which efficiently accounts for the effects of wiring and floorplanning on the area and performance of RT level designs, before the physical design process. Benchmarking has shown that our model is quite accurate.
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ICCAD - Module assignment and interconnect sharing in Register-Transfer synthesis of pipelined data paths
1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers, 1Co-Authors: Nohbyung Park, Fadi J. KurdahiAbstract:The authors present a novel approach to the problem of Register-Transfer (RT) design optimization of pipelined data paths. They perform module assignment with the goal of maximizing the interconnect sharing between RT-level components. The interconnect sharing task is modeled as a constrained clique partitioning problem. They have developed a fast and efficient polynomial time heuristic procedure to solve this problem. This procedure is 30-50 times faster than other existing heuristics while still producing better results for the authors' purposes. >
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EDAC-ETC-EUROASIC - Incorporating the controller effects during Register Transfer level synthesis
Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC, 1Co-Authors: C Ramachandran, Fadi J. KurdahiAbstract:High level synthesis (HLS) has been mainly concerned with datapath synthesis of a digital system. Consequently, controller effects are often ignored when performing HLS tasks. However, the controller may sometimes have significant contributions to the overall system area and delay. Thus, it is necessary to incorporate the controller effects during HLS. Since control synthesis tools such as MISII are time consuming, it is not feasible to synthesize a controller netlist every time a high level design decision is made. As a result, it is necessary to estimate the controller contribution. As a first step towards a comprehensive prediction scheme, we present a simple yet effective controller estimation model which can be invoked during the Register-Transfer synthesis phase of HLS, which attempts to reflect the incremental effects of iterative RT level transformations on the controller area and delay. Our model has been bench-marked and found to efficiently account for the controller area and delay. >
Yoav Etsion - One of the best experts on this subject based on the ideXlab platform.
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hardware description beyond Register Transfer level languages
Field Programmable Gate Arrays, 2020Co-Authors: Oron Port, Yoav EtsionAbstract:Prevalent hardware description languages (HDLs), e.g., Verilog and VHDL, employ Register-Transfer level (RTL) as their underlying programming model. One major downside of the RTL model is that it tightly couples design functionality with timing and device constraints. This coupling increases code complexity and yields code that is more verbose and less portable. High-level synthesis (HLS) tools decouple functionality from timing and design constraints by utilizing constructs from imperative programming languages. These constructs and their sequential semantics, however, impede construction of inherently parallel hardware and data scheduling, which is crucial in many design use-cases. In our work we present a novel dataflow hardware description abstraction layer as basis for hardware design and apply it to DFiant, a Scala-embedded HDL. DFiant leverages dataflow semantics along with modern software language features (e.g., inheritance, polymorphism) and classic HDL traits (e.g., bit-accuracy, input/output ports) to decouple functionality from implementation constraints. Therefore, DFiant designs are timing-agnostic and device-agnostic and can be automatically pipelined by the DFiant compiler to meet target performance requirements. With DFiant we demonstrate how dataflow HDL code can be substantially more portable and compact than its equivalent RTL code, yet without compromising its target design performance.
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FPGA - Hardware Description Beyond Register-Transfer Level Languages
Proceedings of the 2020 ACM SIGDA International Symposium on Field-Programmable Gate Arrays, 2020Co-Authors: Oron Port, Yoav EtsionAbstract:Prevalent hardware description languages (HDLs), e.g., Verilog and VHDL, employ Register-Transfer level (RTL) as their underlying programming model. One major downside of the RTL model is that it tightly couples design functionality with timing and device constraints. This coupling increases code complexity and yields code that is more verbose and less portable. High-level synthesis (HLS) tools decouple functionality from timing and design constraints by utilizing constructs from imperative programming languages. These constructs and their sequential semantics, however, impede construction of inherently parallel hardware and data scheduling, which is crucial in many design use-cases. In our work we present a novel dataflow hardware description abstraction layer as basis for hardware design and apply it to DFiant, a Scala-embedded HDL. DFiant leverages dataflow semantics along with modern software language features (e.g., inheritance, polymorphism) and classic HDL traits (e.g., bit-accuracy, input/output ports) to decouple functionality from implementation constraints. Therefore, DFiant designs are timing-agnostic and device-agnostic and can be automatically pipelined by the DFiant compiler to meet target performance requirements. With DFiant we demonstrate how dataflow HDL code can be substantially more portable and compact than its equivalent RTL code, yet without compromising its target design performance.
Peng Liu - One of the best experts on this subject based on the ideXlab platform.
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hardware trojans detection at Register Transfer level based on machine learning
International Symposium on Circuits and Systems, 2019Co-Authors: Tao Han, Yuze Wang, Peng LiuAbstract:To accurately detect Hardware Trojans in integrated circuits design process, a machine-learning-based detection method at the Register Transfer level (RTL) is proposed. In this method, circuit features are extracted from the RTL source codes and a training database is built using circuits in a Hardware Trojans library. The training database is used to train an efficient detection model based on the gradient boosting algorithm. In order to expand the Hardware Trojans library for detecting new types of Hardware Trojans and update the detection model in time, a server-client mechanism is used. The proposed method can achieve 100% true positive rate and 89% true negative rate, on average, based on the benchmark from Trust-Hub.
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ISCAS - Hardware Trojans Detection at Register Transfer Level Based on Machine Learning
2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019Co-Authors: Tao Han, Yuze Wang, Peng LiuAbstract:To accurately detect Hardware Trojans in integrated circuits design process, a machine-learning-based detection method at the Register Transfer level (RTL) is proposed. In this method, circuit features are extracted from the RTL source codes and a training database is built using circuits in a Hardware Trojans library. The training database is used to train an efficient detection model based on the gradient boosting algorithm. In order to expand the Hardware Trojans library for detecting new types of Hardware Trojans and update the detection model in time, a server-client mechanism is used. The proposed method can achieve 100% true positive rate and 89% true negative rate, on average, based on the benchmark from Trust-Hub.
