The Experts below are selected from a list of 19605 Experts worldwide ranked by ideXlab platform
Kuan-ta Chen - One of the best experts on this subject based on the ideXlab platform.
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Is Server Consolidation Beneficial to MMORPG? A Case Study of World of Warcraft
2010 IEEE 3rd International Conference on Cloud Computing, 2010Co-Authors: Kuan-ta ChenAbstract:MMORPG is shown to be a killer application of Internet, with a global subscriber number increased to 17 millions in 2010. However, MMORPG servers tend to be overly provisioned because 1)such games do not have standard architectures thus dedicated Hardware is assumed; 2) MMORPGs normally adopt a ``sharded design'' to resolve the scalability challenges of content production and workload distribution; and 3) a game is commonly deployed in geographically distributed data centers to protect gamers from excessive network latencies. Therefore, an operator needs to deploy dedicated Hardware for each game in each datacenter, even though Hardware utilization is low. In this paper, we propose a zone-based server consolidation strategy for MMORPGs, which exploits the unique locality property of players' interactions, to cut down the games' considerable Hardware Requirement and energy use. We evaluate the effectiveness of our strategy based on a nine-month trace from a popular MMORPG World of War craft. The evaluation results show that, with a per-hour dynamic zone reallocation policy, the server number required can be reduced by 52% and the total energy consumption can be reduced by 62%, while the user-experienced latency remains undegraded.
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IEEE CLOUD - Is Server Consolidation Beneficial to MMORPG? A Case Study of World of Warcraft
2010 IEEE 3rd International Conference on Cloud Computing, 2010Co-Authors: Kuan-ta ChenAbstract:MMORPG is shown to be a killer application of Internet, with a global subscriber number increased to 17 millions in 2010. However, MMORPG servers tend to be overly provisioned because 1)such games do not have standard architectures thus dedicated Hardware is assumed; 2) MMORPGs normally adopt a ``sharded design'' to resolve the scalability challenges of content production and workload distribution; and 3) a game is commonly deployed in geographically distributed data centers to protect gamers from excessive network latencies. Therefore, an operator needs to deploy dedicated Hardware for each game in each datacenter, even though Hardware utilization is low. In this paper, we propose a zone-based server consolidation strategy for MMORPGs, which exploits the unique locality property of players' interactions, to cut down the games' considerable Hardware Requirement and energy use. We evaluate the effectiveness of our strategy based on a nine-month trace from a popular MMORPG World of War craft. The evaluation results show that, with a per-hour dynamic zone reallocation policy, the server number required can be reduced by 52% and the total energy consumption can be reduced by 62%, while the user-experienced latency remains undegraded.
Paolo Ienne - One of the best experts on this subject based on the ideXlab platform.
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spontaneous reload cache mimicking a larger cache with minimal Hardware Requirement
Networking Architecture and Storages, 2013Co-Authors: Lunkai Zhang, Mingzhe Zhang, Lingjun Fan, Da Wang, Paolo IenneAbstract:In modern processor systems, on-chip Last Level Caches (LLCs) are used to bridge the speed gap between CPUs and off-chip memory. In recent years, the LRU policy effectiveness in low level caches has been questioned. A significant amount of recent work has explored the design space of replacement policies for CPUs' low level cache systems, and proposed a variety of replacement policies. All these pieces of work are based on the traditional idea of a conventional passive cache, which triggers memory accesses exclusively when there is a cache miss. Such passive cache systems have a theoretical performance upper bound, which is represented by Optimal Algorithm. In this work, we introduce a novel cache system called Spontaneous Reload Cache (SR-Cache). Contrary to passive caches, no matter whether a cache access is a hit or miss, an SR-Cache can actively load or reload an off-chip data block which is predicted to be used in the near future and evict the data block which has the lowest probability to be reused soon. We show that, with minimal Hardware overhead, SR-Cache can achieve much better performance than conventional passive caches.
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NAS - Spontaneous Reload Cache: Mimicking a Larger Cache with Minimal Hardware Requirement
2013 IEEE Eighth International Conference on Networking Architecture and Storage, 2013Co-Authors: Lunkai Zhang, Mingzhe Zhang, Lingjun Fan, Da Wang, Paolo IenneAbstract:In modern processor systems, on-chip Last Level Caches (LLCs) are used to bridge the speed gap between CPUs and off-chip memory. In recent years, the LRU policy effectiveness in low level caches has been questioned. A significant amount of recent work has explored the design space of replacement policies for CPUs' low level cache systems, and proposed a variety of replacement policies. All these pieces of work are based on the traditional idea of a conventional passive cache, which triggers memory accesses exclusively when there is a cache miss. Such passive cache systems have a theoretical performance upper bound, which is represented by Optimal Algorithm. In this work, we introduce a novel cache system called Spontaneous Reload Cache (SR-Cache). Contrary to passive caches, no matter whether a cache access is a hit or miss, an SR-Cache can actively load or reload an off-chip data block which is predicted to be used in the near future and evict the data block which has the lowest probability to be reused soon. We show that, with minimal Hardware overhead, SR-Cache can achieve much better performance than conventional passive caches.
R Elangovan - One of the best experts on this subject based on the ideXlab platform.
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reducing Hardware Requirement in fir filter design
International Conference on Acoustics Speech and Signal Processing, 2000Co-Authors: M A Soderstrand, L G Johnson, H Arichanthiran, M D Hoque, R ElangovanAbstract:A Hardware optimization scheme based upon minimum-adder CSD multiplier blocks is combined with a technique for trading adders for delays to reduce Hardware Requirements for fixed-coefficient FIR filters well below that achieved with either technique alone. The technique starts with determining the minimum order filter necessary to meet the filter specifications assuming infinite precision filter coefficients. Then the coefficients are truncated to B bits (which may be specified by the designer) and the order of the filter is increased, if necessary, to meet the filter specifications. From this baseline filter, an exhaustive search is carried out by increasing the filter order (adding delays) and decreasing the bits (decreasing adders) to search for the minimum Hardware. At each search point, the minimum-adder CSD multiplier block approach is used to assure the optimum Hardware realization. The result is the implementation in FPGAs or VLSI of FIR filters with less real estate and/or with less power consumption.
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ICASSP - Reducing Hardware Requirement in FIR filter design
2000 IEEE International Conference on Acoustics Speech and Signal Processing. Proceedings (Cat. No.00CH37100), 1Co-Authors: M A Soderstrand, L G Johnson, H Arichanthiran, M D Hoque, R ElangovanAbstract:A Hardware optimization scheme based upon minimum-adder CSD multiplier blocks is combined with a technique for trading adders for delays to reduce Hardware Requirements for fixed-coefficient FIR filters well below that achieved with either technique alone. The technique starts with determining the minimum order filter necessary to meet the filter specifications assuming infinite precision filter coefficients. Then the coefficients are truncated to B bits (which may be specified by the designer) and the order of the filter is increased, if necessary, to meet the filter specifications. From this baseline filter, an exhaustive search is carried out by increasing the filter order (adding delays) and decreasing the bits (decreasing adders) to search for the minimum Hardware. At each search point, the minimum-adder CSD multiplier block approach is used to assure the optimum Hardware realization. The result is the implementation in FPGAs or VLSI of FIR filters with less real estate and/or with less power consumption.
Lunkai Zhang - One of the best experts on this subject based on the ideXlab platform.
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spontaneous reload cache mimicking a larger cache with minimal Hardware Requirement
Networking Architecture and Storages, 2013Co-Authors: Lunkai Zhang, Mingzhe Zhang, Lingjun Fan, Da Wang, Paolo IenneAbstract:In modern processor systems, on-chip Last Level Caches (LLCs) are used to bridge the speed gap between CPUs and off-chip memory. In recent years, the LRU policy effectiveness in low level caches has been questioned. A significant amount of recent work has explored the design space of replacement policies for CPUs' low level cache systems, and proposed a variety of replacement policies. All these pieces of work are based on the traditional idea of a conventional passive cache, which triggers memory accesses exclusively when there is a cache miss. Such passive cache systems have a theoretical performance upper bound, which is represented by Optimal Algorithm. In this work, we introduce a novel cache system called Spontaneous Reload Cache (SR-Cache). Contrary to passive caches, no matter whether a cache access is a hit or miss, an SR-Cache can actively load or reload an off-chip data block which is predicted to be used in the near future and evict the data block which has the lowest probability to be reused soon. We show that, with minimal Hardware overhead, SR-Cache can achieve much better performance than conventional passive caches.
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NAS - Spontaneous Reload Cache: Mimicking a Larger Cache with Minimal Hardware Requirement
2013 IEEE Eighth International Conference on Networking Architecture and Storage, 2013Co-Authors: Lunkai Zhang, Mingzhe Zhang, Lingjun Fan, Da Wang, Paolo IenneAbstract:In modern processor systems, on-chip Last Level Caches (LLCs) are used to bridge the speed gap between CPUs and off-chip memory. In recent years, the LRU policy effectiveness in low level caches has been questioned. A significant amount of recent work has explored the design space of replacement policies for CPUs' low level cache systems, and proposed a variety of replacement policies. All these pieces of work are based on the traditional idea of a conventional passive cache, which triggers memory accesses exclusively when there is a cache miss. Such passive cache systems have a theoretical performance upper bound, which is represented by Optimal Algorithm. In this work, we introduce a novel cache system called Spontaneous Reload Cache (SR-Cache). Contrary to passive caches, no matter whether a cache access is a hit or miss, an SR-Cache can actively load or reload an off-chip data block which is predicted to be used in the near future and evict the data block which has the lowest probability to be reused soon. We show that, with minimal Hardware overhead, SR-Cache can achieve much better performance than conventional passive caches.
Pramod Kumar Meher - One of the best experts on this subject based on the ideXlab platform.
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scalable approximate dct architectures for efficient hevc compliant video coding
IEEE Transactions on Circuits and Systems for Video Technology, 2017Co-Authors: Maher Jridi, Pramod Kumar MeherAbstract:An approximate kernel for the discrete cosine transform (DCT) of length 4 is derived from the 4-point DCT defined by the High Efficiency Video Coding (HEVC) standard and used for the computation of DCT and inverse DCT (IDCT) of power-of-two lengths. There are two reasons for considering the DCT of length 4 as the basic module. First, it allows computation of DCTs of lengths 4, 8, 16, and 32 prescribed by the HEVC. Second, the DCTs generated by the 4-point DCT not only involve lower complexity, but also offer better compression performance. Fully parallel and area-constrained architectures for the proposed approximate DCT are proposed to have flexible tradeoff between the area and time complexities. In addition, a reconfigurable architecture is proposed where an 8-point DCT can be used in place of a pair of 4-point DCTs. Using the same reconfiguration scheme, a 32-point DCT could be configured for parallel computation of two 16-point DCTs or four 8-point DCTs or eight 4-point DCTs. The proposed reconfigurable design can support real-time coding for high-definition video sequences in the 8k ultrahigh-definition television format ( $7680\times 4320$ at 30 frames/s). A unified forward and inverse transform architecture is also proposed where the Hardware complexity is reduced by sharing Hardware between the DCT and IDCT computations. The proposed approximation has nearly the same arithmetic complexity and Hardware Requirement as those of recently proposed related methods, but involves significantly less error energy and offers better peak signal-to-noise ratio than the others when DCTs of length more than 8 are used. A detailed comparison of the complexity, energy efficiency, and compression performance of different DCT approximation schemes for video coding is also presented. It is shown that the proposed approximation provides a better compressed-image quality than other approximate DCTs. The proposed method can perform HEVC-compliant video coding with marginal degradation of video quality and a slight increase the in bit rate, with a fraction of computational complexity of the latter.
