The Experts below are selected from a list of 40209 Experts worldwide ranked by ideXlab platform
Moisés Vidal Ribeiro - One of the best experts on this subject based on the ideXlab platform.
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narrowband hybrid plc wireless transceiver prototype Hardware Resource usage and energy consumption
Ad Hoc Networks, 2019Co-Authors: Vinicius Lagrota Rodrigues Da Costa, Victor Fernandes, Moisés Vidal RibeiroAbstract:Abstract This work discusses a prototype of the so-called narrowband (NB) hybrid power line communication (PLC)/Wireless transceiver, which jointly uses parallel power line and wireless channels for providing data communication to the Industry 4.0, Smart Grids and the Internet of Things applications. The prototype introduces a modified version of the IEEE 1901.2 Standard, which was designed to fulfill NB - PLC applications, to implement the media access control (MAC) sublayer and the physical (PHY) layer of a hybrid transceiver that is capable of transmitting data through both power line and wireless channels. Therefore, the NB hybrid PLC/Wireless transceiver prototype is compatible with a NB - PLC transceiver that makes use of the IEEE 1901.2 Standard. Moreover, both transceivers can constitute heterogeneous data communication networks that are capable of improving reliability and coverage. Furthermore, based on a field-programmable gate array (FPGA) device, we discuss the Hardware Resource usage and energy consumption analyses and the Hardware feasibility of implementing a bit correction technique at the link layer of the NB hybrid PLC/Wireless transceiver prototype. We show that the signal/data processing block of the proposed transceiver demands only 1.12 times the energy consumption required by a NB - PLC transceiver based on the IEEE 1901.2 Standard. Moreover, the designed roadmap for this kind of hybrid PLC/wireless transceiver demands 1.5 times the Hardware Resource usage in comparison to the implementation of the PLC transceiver based on the IEEE 1901.2 Standard. Finally, we show that up 5 bits can be corrected at the link layer level without increasing the clock frequency.
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Narrowband hybrid PLC/wireless: Transceiver prototype, Hardware Resource usage and energy consumption
Ad Hoc Networks, 2019Co-Authors: Vinícius Lagrota Rodrigues Da Costa, Victor Fernandes, Moisés Vidal RibeiroAbstract:This work discusses a prototype of the so-called narrowband (NB) hybrid power line communication (PLC)/Wireless transceiver, which jointly uses parallel power line and wireless channels for providing data communication to the Industry 4.0, Smart Grids and the Internet of Things applications. The prototype introduces a modified version of the IEEE 1901.2 Standard, which was designed to fulfill NB - PLC applications, to implement the media access control (MAC) sublayer and the physical (PHY) layer of a hybrid transceiver that is capable of transmitting data through both power line and wireless channels. Therefore, the NB hybrid PLC/Wireless transceiver prototype is compatible with a NB - PLC transceiver that makes use of the IEEE 1901.2 Standard. Moreover, both transceivers can constitute heterogeneous data communication networks that are capable of improving reliability and coverage. Furthermore, based on a field-programmable gate array (FPGA) device, we discuss the Hardware Resource usage and energy consumption analyses and the Hardware feasibility of implementing a bit correction technique at the link layer of the NB hybrid PLC/Wireless transceiver prototype. We show that the signal/data processing block of the proposed transceiver demands only 1.12 times the energy consumption required by a NB - PLC transceiver based on the IEEE 1901.2 Standard. Moreover, the designed roadmap for this kind of hybrid PLC/wireless transceiver demands 1.5 times the Hardware Resource usage in comparison to the implementation of the PLC transceiver based on the IEEE 1901.2 Standard. Finally, we show that up 5 bits can be corrected at the link layer level without increasing the clock frequency.
Alexander Schill - One of the best experts on this subject based on the ideXlab platform.
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analysis of the power and Hardware Resource consumption of servers under different load balancing policies
International Conference on Cloud Computing, 2012Co-Authors: Waltenegus Dargie, Alexander SchillAbstract:Most Internet applications employ some kind of load balancing policies in a cluster setting to achieve reliable service provision as well as to deal with a Resource bottleneck. However, these policies may not ensure the utilization of \textit{all} of the Hardware Resources in a server equally efficiently. This paper experimentally investigates the relationship between the power consumption and Resource utilization of a multimedia server cluster when different load balancing policies are used to distribute a workload. Our observations are the following: (1) A bottleneck on a single Hardware Resource can lead to a significant amount of underutilization of the entire system. (2) A ten times increment in the network bandwidth of the entire cluster can double the throughput of individual servers. The associated increment in power consumption of the individual servers is 1.2\% only. (3) For TCP-based applications, session information is more useful than other types of status information to utilize power more efficiently. (4) The use of dynamic frequency scaling does not affect the overall throughput of IO-bound applications but reduces the power consumption of the servers; but this reduction is only 12% of the overall power consumption. More power can be saved by avoiding a Resource bottleneck or through service consolidation.
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IEEE CLOUD - Analysis of the Power and Hardware Resource Consumption of Servers under Different Load Balancing Policies
2012 IEEE Fifth International Conference on Cloud Computing, 2012Co-Authors: Waltenegus Dargie, Alexander SchillAbstract:Most Internet applications employ some kind of load balancing policies in a cluster setting to achieve reliable service provision as well as to deal with a Resource bottleneck. However, these policies may not ensure the utilization of \textit{all} of the Hardware Resources in a server equally efficiently. This paper experimentally investigates the relationship between the power consumption and Resource utilization of a multimedia server cluster when different load balancing policies are used to distribute a workload. Our observations are the following: (1) A bottleneck on a single Hardware Resource can lead to a significant amount of underutilization of the entire system. (2) A ten times increment in the network bandwidth of the entire cluster can double the throughput of individual servers. The associated increment in power consumption of the individual servers is 1.2\% only. (3) For TCP-based applications, session information is more useful than other types of status information to utilize power more efficiently. (4) The use of dynamic frequency scaling does not affect the overall throughput of IO-bound applications but reduces the power consumption of the servers; but this reduction is only 12% of the overall power consumption. More power can be saved by avoiding a Resource bottleneck or through service consolidation.
Mohamed Abid - One of the best experts on this subject based on the ideXlab platform.
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Hardware Resource estimation for heterogeneous fpga based socs
Symposium on Applied Computing, 2017Co-Authors: Mariem Makni, Mouna Baklouti, Smail Niar, Mohamed AbidAbstract:The increasing complexity of recent System-on-Chip (SoC) designs introduces new challenges for design space exploration tools. In addition to the time-to-market challenge, designers need to estimate rapidly and accurately both performance and area occupation of complex and diverse applications. High-Level Synthesis (HLS) has been emerged as an attractive solution for designers to address these challenges in order to explore a large number of SoC configurations. In this paper, we target hybrid CPU-FPGA based SoCs. We propose a high-level area estimation tool based on an analytic model without requiring register-transfer level (RTL) implementations. This technique allows to estimate the required FPGA Resources at the source code level to map an application to a hybrid CPU-FPGA system. The proposed model also enables a fast design exploration with different trade-offs through HLS optimization pragmas. Experimental results show that the proposed area analytic model provides an accurate estimation with a negligible error (less than 5+) compared to RTL implementations.
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SAC - Hardware Resource estimation for heterogeneous FPGA-based SoCs
Proceedings of the Symposium on Applied Computing, 2017Co-Authors: Mariem Makni, Mouna Baklouti, Smail Niar, Mohamed AbidAbstract:The increasing complexity of recent System-on-Chip (SoC) designs introduces new challenges for design space exploration tools. In addition to the time-to-market challenge, designers need to estimate rapidly and accurately both performance and area occupation of complex and diverse applications. High-Level Synthesis (HLS) has been emerged as an attractive solution for designers to address these challenges in order to explore a large number of SoC configurations. In this paper, we target hybrid CPU-FPGA based SoCs. We propose a high-level area estimation tool based on an analytic model without requiring register-transfer level (RTL) implementations. This technique allows to estimate the required FPGA Resources at the source code level to map an application to a hybrid CPU-FPGA system. The proposed model also enables a fast design exploration with different trade-offs through HLS optimization pragmas. Experimental results show that the proposed area analytic model provides an accurate estimation with a negligible error (less than 5+) compared to RTL implementations.
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Hardware Resource utilization optimization in FPGA-based Heterogeneous MPSoC architectures
Microprocessors and Microsystems, 2015Co-Authors: Bouthaina Dammak, Mouna Baklouti, Smail Niar, Rachid Benmansour, Mohamed AbidAbstract:Next generation FPGA circuits will allow the integration of dozens of hard and soft cores as well as dedicated accelerators in the same chip. These Heterogeneous Multiprocessor System-on-Chip (Ht-MPSoC) architectures will allow the design of very complex System-on-Chips (SoC) on a single FPGA chip and will fulfill modern application requirements, in terms of performance/energy consumption ratio. In this paper, we extend existing FPGA-based Ht-MPSoC architectures by considering sharing Hardware accelerators among the cores. In these architectures, cores on the FPGA may have different Resources that can be shared in different manners. To explore the large space of possible configurations of Ht-MPSoC on FPGA, designer needs a fast and accurate exploration tool. For this reason, a Mixed Integer Programming (MIP) model is also proposed to determine the Ht-MPSoC configuration that consumes the least HW Resources while respecting the application execution time constraints. Using our MIP model, the design space of several hundreds of private and shared HW accelerators can be explored in a reasonable time with high accuracy.
Liang-gee Chen - One of the best experts on this subject based on the ideXlab platform.
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ISCAS - System Bandwidth Analysis of Multiview Video Coding with Precedence Constraint
2007 IEEE International Symposium on Circuits and Systems, 2007Co-Authors: Pei-kuei Tsung, Li-fu Ding, Wei-yin Chen, Tung-chien Chen, Shao-yi Chien, Liang-gee ChenAbstract:Multiview video coding (MVC) systems require much more bandwidth and computational complexity relative to mono-view video systems. Thus, when designing a VLSI architecture for MVC systems, the Hardware Resource allocation is a critical issue. In this paper, we propose a new system bandwidth analysis scheme for various and complicated MVC structures. The precedence constraint in the graph theory is adopted for deriving the processing order of frames in a MVC system. In addition, current block centric scheduling (CBCS) and search window centric scheduling (SWCS) are proposed for MVC bandwidth analysis. By adopting data reuse schemes, several design points are explored with the aid of the proposed analysis scheme. The suitable Hardware Resource allocation can be easily determined.
Jan Madsen - One of the best experts on this subject based on the ideXlab platform.
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Hardware Resource allocation for Hardware software partitioning in the lycos system
Design Automation and Test in Europe, 1998Co-Authors: Jesper Nicolai Riis Grode, Peter Voigt Knudsen, Jan MadsenAbstract:This paper presents a novel Hardware Resource allocation technique for Hardware/software partitioning. It allocates Hardware Resources to the Hardware data-path using information such as data-dependencies between operations in the application, and profiling information. The algorithm is useful as a designer's/design tool's aid to generate good Hardware allocations for use in Hardware/software partitioning. The algorithm has been implemented in a tool under the LYCOS system. The results show that the allocations produced by the algorithm come close to the best allocations obtained by exhaustive search.
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DATE - Hardware Resource allocation for Hardware/software partitioning in the LYCOS system
Proceedings Design Automation and Test in Europe, 1998Co-Authors: Jesper Nicolai Riis Grode, Peter Voigt Knudsen, Jan MadsenAbstract:This paper presents a novel Hardware Resource allocation technique for Hardware/software partitioning. It allocates Hardware Resources to the Hardware data-path using information such as data-dependencies between operations in the application, and profiling information. The algorithm is useful as a designer's/design tool's aid to generate good Hardware allocations for use in Hardware/software partitioning. The algorithm has been implemented in a tool under the LYCOS system. The results show that the allocations produced by the algorithm come close to the best allocations obtained by exhaustive search.
