The Experts below are selected from a list of 2706 Experts worldwide ranked by ideXlab platform
Michel Cand - One of the best experts on this subject based on the ideXlab platform.
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VLSI Architecture for digital processing of speech signals
Annales Des Télécommunications, 1993Co-Authors: Patrice Le Scan, Marc Soler, Michel CandAbstract:Les applications de traitement du signal audio en télécommunications et plus particulièrement en compression extension du débit binaire sont de plus en plus performantes. Les réalisations en circuits intégrés vlsi correspondantes sont de plus en plus complexes. Les solutions actuelles sont développées essentiellement soit autour ďun processeur standard de traitement numérique du signal microprogrammé, soit autour ďun cŒur de processeur et de macrofonctions paramétrables. Ces solutions ne réspondent pas complètement à une application pour laquelle les spécifications fondamentales sont la surface de silicium et la consommation minimales du circuit. La solution décrite est basée sur une Architecture de processeur paramétrable type Harvard et un compilateur C permettant ďobtenir un microcode exécutable optimisé pour cette Architecture. Deux exemples ďapplications traités par la méthode sont décrits. Due to the evolution of increasingly high performant dsp algorithms for bit rate reduction of speech signals in telecommunications, vlsi implementations of these applications are becoming more and more complex. The solutions currently being used for these applications are general purpose digital signal processors or dsp cores which are never fully adapted to the application in terms of vlsi Architecture, i.e. silicon area and power consumption. We propose an alternative to these solutions, based on a parametrable Harvard Architecture, and a C compiler which gives an optimized microcode suited to this Architecture and to the application. Finally we present two examples of audio applications implemented using this solution.
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VLSI Architecture for digital processing of speech signals
Annales Des Télécommunications, 1993Co-Authors: Patrice Le Scan, Marc Soler, Michel CandAbstract:Due to the evolution of increasingly high performantdsp algorithms for bit rate reduction of speech signals in telecommunications,vlsi implementations of these applications are becoming more and more complex. The solutions currently being used for these applications are general purpose digital signal processors or dsp cores which are never fully adapted to the application in terms ofvlsi Architecture, i.e. silicon area and power consumption. We propose an alternative to these solutions, based on a parametrable Harvard Architecture, and a C compiler which gives an optimized microcode suited to this Architecture and to the application. Finally we present two examples of audio applications implemented using this solution.
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A GSM Vocoder using a flexible DSP core
ESSCIRC '92: Eighteenth European Solid-State Circuits conference, 1992Co-Authors: Michel Cand, B. Conq, M. Soler, B. Bocaert, A. KuntzAbstract:We present a speech vocoder that will be used in GSM mobile systems to convert 300-3400 Hz speech to 13 Kbit/s digital bit stream. This 350 000 transistor chip was designed in a CMOS 1.0 ?m technology in collaboration with VLSI Technology. The Architecture was defined with a flexible 13 MHz DSP core developped at CNET. The GSM 06 series recommendations are met with a low 2.7 MIps. The DSP core has a VLIW microprogrammed Harvard Architecture. The ROM program is obtained without writing assembler using a C-to-microcode compiler targeted to the Architecture.
Yu Zhang - One of the best experts on this subject based on the ideXlab platform.
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Modeling and simulation of yard trailer dispatching at container terminals
2009 IEEE International Conference on Automation and Logistics, 2009Co-Authors: Bin Li, Yu Zhang, Wen-feng Li, Yan-hong Ge, Huan Chen, Xiao-lei LiangAbstract:The trend that container ships become increasing large-scale and fast-sailing brings forward the more severe requirements to container terminal logistics system (CTLS) than ever. Whether yard trailer dispatching at container terminals is sound or not possesses of important significance to improve on the integrated operational efficiency of CTLS. So this paper utilizes hybrid flow shop with blocking based on attributes to build the mathematical model of yard trailer dynamic dispatching and presents the corresponding formalization model based on Harvard Architecture and multi-agent. Both structure a self-contained modeling Architecture for CTLS, which not only serves the turn to yard trailer dispatching but also to the other handling sections in CTLS. The following simulations using AnyLogic and SQL Server 2005 validate the feasibility and creditability of the above modeling methodology and provide a scientific basis and engineering way for the improvement of CTLS.
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Container terminal scheduling and decision-making using simulation based optimization and business intelligence
2008 IEEE International Conference on Mechatronics and Automation, 2008Co-Authors: Yu ZhangAbstract:Scheduling and decision-making in container terminal logistics system (CTLS) has been the focus of research and application. This paper remodels the operation of CTLS through advancing an innovative multilevel control and feedback framework and methodology. That utilizes the knowledge engine which lies in business intelligence platform to drive the simulation and optimization engine indwelling in the simulation based optimization tool which drives the operation of port ultimately. At the same time, the whole CTLS is modeled by agent-based computing, and the production and scheduling section is based on the Harvard Architecture, which serves the turn to solve scheduling and decision-making in the complex system and makes the modeling to process of outstanding agility and robustness. This methodology roots in pervasive computing deeply and helps the executors and managers in port to constitute the scheduling plan and support important decision. Finally, an applied instance on the berth allocation and an equipment layout analysis to support decision are demonstrated to validate the feasibility and creditability of the methodology.
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Range image processing in real time based on digital signal processor
Optical Manufacturing Technologies, 2002Co-Authors: Yuanhan Jin, Wenyao Liu, Wei Zheng, Yu ZhangAbstract:Laser radar is a distance measurement system, which makes laser range scanning and receives echo signal is order to get range images. Digital signal processors (DSPs) are based on an advanced modified Harvard Architecture and a pipeline operation. TI DSPs have characteristics made them the ideal choice for a wide range of processing applications and Architectures designed specifically for real-time signal processing. In this paper, range image segmentation method based on the basis operation of mathematical morphologly and an estimation algorithm based on adaptive surface fitting and robust M-estimation is proposed. The segmentation and estimation algorithm was applied successfully to many real range images; the processing speed and noise immunity is better than traditional methods.
Patrice Le Scan - One of the best experts on this subject based on the ideXlab platform.
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VLSI Architecture for digital processing of speech signals
Annales Des Télécommunications, 1993Co-Authors: Patrice Le Scan, Marc Soler, Michel CandAbstract:Due to the evolution of increasingly high performantdsp algorithms for bit rate reduction of speech signals in telecommunications,vlsi implementations of these applications are becoming more and more complex. The solutions currently being used for these applications are general purpose digital signal processors or dsp cores which are never fully adapted to the application in terms ofvlsi Architecture, i.e. silicon area and power consumption. We propose an alternative to these solutions, based on a parametrable Harvard Architecture, and a C compiler which gives an optimized microcode suited to this Architecture and to the application. Finally we present two examples of audio applications implemented using this solution.
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VLSI Architecture for digital processing of speech signals
Annales Des Télécommunications, 1993Co-Authors: Patrice Le Scan, Marc Soler, Michel CandAbstract:Les applications de traitement du signal audio en télécommunications et plus particulièrement en compression extension du débit binaire sont de plus en plus performantes. Les réalisations en circuits intégrés vlsi correspondantes sont de plus en plus complexes. Les solutions actuelles sont développées essentiellement soit autour ďun processeur standard de traitement numérique du signal microprogrammé, soit autour ďun cŒur de processeur et de macrofonctions paramétrables. Ces solutions ne réspondent pas complètement à une application pour laquelle les spécifications fondamentales sont la surface de silicium et la consommation minimales du circuit. La solution décrite est basée sur une Architecture de processeur paramétrable type Harvard et un compilateur C permettant ďobtenir un microcode exécutable optimisé pour cette Architecture. Deux exemples ďapplications traités par la méthode sont décrits. Due to the evolution of increasingly high performant dsp algorithms for bit rate reduction of speech signals in telecommunications, vlsi implementations of these applications are becoming more and more complex. The solutions currently being used for these applications are general purpose digital signal processors or dsp cores which are never fully adapted to the application in terms of vlsi Architecture, i.e. silicon area and power consumption. We propose an alternative to these solutions, based on a parametrable Harvard Architecture, and a C compiler which gives an optimized microcode suited to this Architecture and to the application. Finally we present two examples of audio applications implemented using this solution.
Marc Soler - One of the best experts on this subject based on the ideXlab platform.
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VLSI Architecture for digital processing of speech signals
Annales Des Télécommunications, 1993Co-Authors: Patrice Le Scan, Marc Soler, Michel CandAbstract:Due to the evolution of increasingly high performantdsp algorithms for bit rate reduction of speech signals in telecommunications,vlsi implementations of these applications are becoming more and more complex. The solutions currently being used for these applications are general purpose digital signal processors or dsp cores which are never fully adapted to the application in terms ofvlsi Architecture, i.e. silicon area and power consumption. We propose an alternative to these solutions, based on a parametrable Harvard Architecture, and a C compiler which gives an optimized microcode suited to this Architecture and to the application. Finally we present two examples of audio applications implemented using this solution.
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VLSI Architecture for digital processing of speech signals
Annales Des Télécommunications, 1993Co-Authors: Patrice Le Scan, Marc Soler, Michel CandAbstract:Les applications de traitement du signal audio en télécommunications et plus particulièrement en compression extension du débit binaire sont de plus en plus performantes. Les réalisations en circuits intégrés vlsi correspondantes sont de plus en plus complexes. Les solutions actuelles sont développées essentiellement soit autour ďun processeur standard de traitement numérique du signal microprogrammé, soit autour ďun cŒur de processeur et de macrofonctions paramétrables. Ces solutions ne réspondent pas complètement à une application pour laquelle les spécifications fondamentales sont la surface de silicium et la consommation minimales du circuit. La solution décrite est basée sur une Architecture de processeur paramétrable type Harvard et un compilateur C permettant ďobtenir un microcode exécutable optimisé pour cette Architecture. Deux exemples ďapplications traités par la méthode sont décrits. Due to the evolution of increasingly high performant dsp algorithms for bit rate reduction of speech signals in telecommunications, vlsi implementations of these applications are becoming more and more complex. The solutions currently being used for these applications are general purpose digital signal processors or dsp cores which are never fully adapted to the application in terms of vlsi Architecture, i.e. silicon area and power consumption. We propose an alternative to these solutions, based on a parametrable Harvard Architecture, and a C compiler which gives an optimized microcode suited to this Architecture and to the application. Finally we present two examples of audio applications implemented using this solution.
R. Ernst - One of the best experts on this subject based on the ideXlab platform.
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Long pipelines in single-chip digital signal processors-concepts and case study
IEEE Transactions on Circuits and Systems, 1991Co-Authors: R. ErnstAbstract:The effectiveness of long pipelines in single-chip digital signal processors for complex algorithms was studied using a processor model with 25 pipeline stages. The processor is based on a Harvard Architecture. Pipelining is used to reduce the instruction cycle time compared to current signal processors. Key features of the processor model are data-stationary pipeline control, local resolution of pipeline hazards with buffering, multiple branch prediction, a mixed relative-incremental addressing scheme, and asynchronous communication between pipeline and environment. The processor is implemented as a software model. The results show that high pipeline utilization can be achieved for a variety of algorithms leading to a significantly higher performance than achieved by conventional single-chip signal processors with Harvard Architecture. >
