The Experts below are selected from a list of 51 Experts worldwide ranked by ideXlab platform
Yorgos Christoforou - One of the best experts on this subject based on the ideXlab platform.
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A new method for multiplying the Miller capacitance using active components
2020Co-Authors: G. De Cremoux, Yorgos ChristoforouAbstract:We present in this paper a new design method for increasing the multiplication factor of the Miller capacitance, using active components. This is achieved by connecting the output of the Miller capacitor on a High Impedance Node and then buffer it to the output of the first gain stage. One can then achieve a very big Miller capacitance multiplication factor, making it possible to efficiently use the Miller effect. This technique has been used to realize a low drop-out regulator which remains stable for very High capacitive loads due exactly to this active Miller multiplication technique.
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A new method for multiplying the Miller capacitance using active components [voltage regulator example]
Proceedings of the IEEE 2003 Custom Integrated Circuits Conference 2003., 2003Co-Authors: G. De Cremoux, Yorgos ChristoforouAbstract:We present in this paper a new design method for increasing the multiplication factor of the Miller capacitance, using active components. This is achieved by connecting the output of the Miller capacitor on a High Impedance Node and then buffering it to the output of the first gain stage. One can then achieve a very large Miller capacitance multiplication factor, making it possible to efficiently use the Miller effect. This technique has been used to realize a low drop-out regulator which remains stable for very High capacitive loads due exactly to this active Miller multiplication technique.
G. De Cremoux - One of the best experts on this subject based on the ideXlab platform.
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A new method for multiplying the Miller capacitance using active components
2020Co-Authors: G. De Cremoux, Yorgos ChristoforouAbstract:We present in this paper a new design method for increasing the multiplication factor of the Miller capacitance, using active components. This is achieved by connecting the output of the Miller capacitor on a High Impedance Node and then buffer it to the output of the first gain stage. One can then achieve a very big Miller capacitance multiplication factor, making it possible to efficiently use the Miller effect. This technique has been used to realize a low drop-out regulator which remains stable for very High capacitive loads due exactly to this active Miller multiplication technique.
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A new method for multiplying the Miller capacitance using active components [voltage regulator example]
Proceedings of the IEEE 2003 Custom Integrated Circuits Conference 2003., 2003Co-Authors: G. De Cremoux, Yorgos ChristoforouAbstract:We present in this paper a new design method for increasing the multiplication factor of the Miller capacitance, using active components. This is achieved by connecting the output of the Miller capacitor on a High Impedance Node and then buffering it to the output of the first gain stage. One can then achieve a very large Miller capacitance multiplication factor, making it possible to efficiently use the Miller effect. This technique has been used to realize a low drop-out regulator which remains stable for very High capacitive loads due exactly to this active Miller multiplication technique.
Jaume Segura - One of the best experts on this subject based on the ideXlab platform.
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VTS - Stuck-Open Fault Leakage and Testing in Nanometer Technologies
2009 27th IEEE VLSI Test Symposium, 2009Co-Authors: J. C. Vazquez, Victor Champac, Chuck Hawkins, Jaume SeguraAbstract:The stuck-open fault (SOF) is a difficult, hard failure mechanism unique to CMOS technology. Its detection requires a specific 2-vector pair that examines each transistor in the logic gate for an open defect in its drain and/or source. In this work it is shown that this failure mechanism is very alive and relevant to modern technologies. The small nanometer technology capacitances and the increased leakage currents result in faster discharges of the floating High Impedance Node making fault detection more difficult. A test vector strategy is proposed to improve the detection of this fault for technologies with gate current leakage.
Ramesh Harjani - One of the best experts on this subject based on the ideXlab platform.
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All MOSCAP Based Continuously Tunable Filter
Analog Circuits and Signal Processing, 2016Co-Authors: Rakesh Kumar Palani, Ramesh HarjaniAbstract:This chapter presents an inverter based filter design that uses only MOSCAP as filter capacitors. Further in the design the load capacitance compensates the negative feedback network allowing the majority of current to flow into the load. This results in an increase in the overall power efficiency. As a proof of concept, a third order inverter based 34–314 MHz tunable continuous time channel select filter for software-defined radios is fabricated in TSMC’s 65 nm technology. By using the High density tunable MOSCAPs at a low swing Node, the filter achieves an OIP3 of +25.24 dBm while drawing 4.2 mA from a 1.1 V supply and occupies an area of 0.007 mm2. The measured intermodulation distortion varies by 5 dB across a 120∘ variation in temperature and 6.5 dB across a 200 mV variation in power supply. Further, the filter presents a High Impedance Node at the input and a low Impedance Node at the output easing system integration.
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CICC - A 4.6mW, 22dBm IIP3 all MOSCAP based 34–314MHz tunable continuous time filter in 65nm
2015 IEEE Custom Integrated Circuits Conference (CICC), 2015Co-Authors: Rakesh Kumar Palani, Ramesh HarjaniAbstract:A inverter based filter design is proposed that uses only MOSCAPs as filter capacitors. Further in the design the load capacitance compensates the negative feedback network allowing the majority of current to flow into the load. This results in an increase in the overall power efficiency. As a proof of concept, a 3rd order inverter based 34–314 MHz tunable continuous time channel select filter for software-defined radios is fabricated in TSMCs 65nm technology. By using the High density tunable MOSCAPs at a low swing Node, the filter achieves an OIP3 of +25.24 dBm while drawing 4.2mA from a 1.1V supply and occupies an area of 0.007mm2. The measured intermodulation distortion varies by 5dB across a 120° variation in temperature and 6.5dB across a 200mV variation in power supply. Further, the filter presents a High Impedance Node at the input and a low Impedance Node at the output easing system integration.
J. C. Vazquez - One of the best experts on this subject based on the ideXlab platform.
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VTS - Stuck-Open Fault Leakage and Testing in Nanometer Technologies
2009 27th IEEE VLSI Test Symposium, 2009Co-Authors: J. C. Vazquez, Victor Champac, Chuck Hawkins, Jaume SeguraAbstract:The stuck-open fault (SOF) is a difficult, hard failure mechanism unique to CMOS technology. Its detection requires a specific 2-vector pair that examines each transistor in the logic gate for an open defect in its drain and/or source. In this work it is shown that this failure mechanism is very alive and relevant to modern technologies. The small nanometer technology capacitances and the increased leakage currents result in faster discharges of the floating High Impedance Node making fault detection more difficult. A test vector strategy is proposed to improve the detection of this fault for technologies with gate current leakage.