The Experts below are selected from a list of 31977 Experts worldwide ranked by ideXlab platform

Kaushik Roy - One of the best experts on this subject based on the ideXlab platform.

  • Area-Efficient SOT-MRAM With a Schottky Diode
    IEEE Electron Device Letters, 2016
    Co-Authors: Yeongkyo Seo, Kon-woo Kwon, Kaushik Roy
    Abstract:

    This letter presents a spin-orbit torque magnetic random access memory (SOT-MRAM) for High-Density, reliable, and energy-efficient on-chip memory application. Unlike the conventional SOT-MRAM requiring two access transistors, the proposed MRAM uses only one access transistor along with a Schottky diode in order to achieve High Integration Density while maintaining the advantages of SOT-MRAM, such as low write energy and enhanced reliability of magnetic tunnel junction. The Schottky diode is forward-biased during read, whereas it is reverse-biased during write to prevent sneak current paths. Our simulation results show that the proposed MRAM can achieve 30% and 50% reduction in bit-cell area in comparison to conventional spin-transfer torque MRAM (STT-MRAM) and SOT-MRAM, respectively, and $\sim 2.5\times $ improvement in write power compared with the STT-MRAM.

  • Spin-Based Neuron Model With Domain-Wall Magnets as Synapse
    IEEE Transactions on Nanotechnology, 2012
    Co-Authors: Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
    Abstract:

    We present artificial neural network design using spin devices that achieves ultralow voltage operation, low power consumption, High speed, and High Integration Density. We employ spin torque switched nanomagnets for modeling neuron and domain-wall magnets for compact, programmable synapses. The spin-based neuron-synapse units operate locally at ultralow supply voltage of 30 mV resulting in low computation power. CMOS-based interneuron communication is employed to realize network-level functionality. We corroborate circuit operation with physics-based models developed for the spin devices. Simulation results for character recognition as a benchmark application show 95% lower power consumption as compared to 45-nm CMOS design.

Georgios Panagopoulos - One of the best experts on this subject based on the ideXlab platform.

  • write optimized reliable design of stt mram
    International Symposium on Low Power Electronics and Design, 2012
    Co-Authors: Sumeet Kumar Gupta, Sang Phill Park, Georgios Panagopoulos
    Abstract:

    Spin transfer torque magnetic random access memory (STT MRAM) is a promising non-volatile memory due to its outstanding potential for High Integration Density and excellent scalability. Despite the attractive features, High write current and power is still a major challenge. As a result, the optimization of the memory for write is critical. In this work, we analyze asymmetric write currents in STT MRAMs considering process variations, and identify a potential for write power reduction. We propose circuit design techniques 1) bit-line voltage clamping using a pass transistor and 2) 2T-1R dual source-line bit-cell design, to balance out the asymmetric write currents and optimize the memory design from both write-power and reliability aspects. Our proposed techniques can be easily incorporated with previously proposed design techniques without affecting the bit-cell write-ability, read stability, and performance. We analyze the impact of our proposed techniques on write power and MTJ current Density and show 30-68% average write power savings and 4-41% reduction in MTJ current Density in STT MRAM.

  • Spin-Based Neuron Model With Domain-Wall Magnets as Synapse
    IEEE Transactions on Nanotechnology, 2012
    Co-Authors: Mrigank Sharad, Charles Augustine, Georgios Panagopoulos, Kaushik Roy
    Abstract:

    We present artificial neural network design using spin devices that achieves ultralow voltage operation, low power consumption, High speed, and High Integration Density. We employ spin torque switched nanomagnets for modeling neuron and domain-wall magnets for compact, programmable synapses. The spin-based neuron-synapse units operate locally at ultralow supply voltage of 30 mV resulting in low computation power. CMOS-based interneuron communication is employed to realize network-level functionality. We corroborate circuit operation with physics-based models developed for the spin devices. Simulation results for character recognition as a benchmark application show 95% lower power consumption as compared to 45-nm CMOS design.

Mi Miao - One of the best experts on this subject based on the ideXlab platform.

  • a vacuum airtight package with multifunctional ltcc substrate and integrated pirani vacuum gauge for 3d sip Integration applications
    IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010
    Co-Authors: Mi Miao
    Abstract:

    This paper reports the design and initial experimental investigation of a vacuum/airtight package, based on a multilayered LTCC substrate that acts not only as a chip carrier with flexible interconnects but an integrated panel with multiple functional structure. Design, validation and experimental results for various cooling microchannels embedded into the substrate are presented; the substrate temperature rise is cut by over 70% compared with substrate without microchannels. The effect of vacuum on cooling is simulated. A hot-wire micro Pirani gauge are integrated onto the substrate by wire bonding for a simple and effective in-situ vacuum measuring. The packaged sample display a leakage rate of lower than 10 −12 Pa · m3/s. Therefore, this packaging can be an optimal choice for 3D system-in-package applications demanding High Integration Density, medium vacuum circumstance and long usage/storage lifecycle.

  • A vacuum/airtight package with multifunctional LTCC substrate and integrated Pirani vacuum gauge for 3D SIP Integration applications
    2010
    Co-Authors: Mi Miao, Ji Yufeng, Ga Hua, Li Zhensong
    Abstract:

    This paper reports the design and initial experimental investigation of a vacuum/airtight package, based on a multilayered LTCC substrate that acts not only as a chip carrier with flexible interconnects but an integrated panel with multiple functional structure. Design, validation and experimental results for various cooling microchannels embedded into the substrate are presented; the substrate temperature rise is cut by over 70% compared with substrate without microchannels. The effect of vacuum on cooling is simulated. A hot-wire micro Pirani gauge are integrated onto the substrate by wire bonding for a simple and effective in-situ vacuum measuring. The packaged sample display a leakage rate of lower than 10-12 Pa &middot m3/s. Therefore, this packaging can be an optimal choice for 3D system-in-package applications demanding High Integration Density, medium vacuum circumstance and long usage/storage lifecycle. ?2010 IEEE.EI

A. Driessen - One of the best experts on this subject based on the ideXlab platform.

  • Design, tolerance analysis, and fabrication of silicon oxynitride based planar optical waveguides for communication devices
    Journal of Lightwave Technology, 1999
    Co-Authors: K. Worhoff, P.v. Lambeck, A. Driessen
    Abstract:

    Planar optical waveguiding structures for application in communication networks are Highly demanding with respect to low insertion loss, efficient fiber-to-chip coupling, polarization independent operation, High Integration Density, reliable fabrication, and last but not least cost efficiency. When applying silicon oxynitride, which is a very versatile material, planar waveguiding structures can be designed having the potential of meeting all those requirements. In this paper, we will describe the design of such a waveguiding structure, demonstrate the practical feasibility of realizing this structure and discuss the preliminary measurement results.

Gang Quan - One of the best experts on this subject based on the ideXlab platform.

  • a statistical stt ram retention model for fast memory subsystem designs
    Asia and South Pacific Design Automation Conference, 2017
    Co-Authors: Zihao Liu, Wujie Wen, Lei Jiang, Yier Jin, Gang Quan
    Abstract:

    Spin-transfer torque random access memory (STT-RAM) is a promising nonvolatile memory (NVM) solution to implement on-chip caches and off-chip main memories for its High Integration Density and short access time, but it suffers from considerable write latency and energy overhead. Aggressively relaxing its non-volatility for write fast and write energy efficient memory subsystems has been quite debatable, due to the unclear retention behavior on a timescale of microseconds-to-seconds. Moreover, recent studies project that retention failure will eventually dominate the cell reliability as STT-RAM scales. As a result, a comprehensive understanding of the thermal noise induced STT-RAM retention mechanism has become a must. In this work, we develop a compact semi-analytical model for fast retention failure analysis. We then systematically analyze critical factors (e.g., initial angle, device dimension etc.) and their impacts on the STT-RAM retention behavior through our model. Our experimental results show that STT-RAM suffers from a soft-error style retention failure, which may happen instantly just after the last write finishes and is totally different from that of DRAM and Flash, i.e., the gradual charge loss process. Our model offers an excellent agreement with the results from golden macro-magnetic simulations in the region of interest without conducting expensive Monte-Carlo runs. At last, we demonstrate our model can enable architectural designers to rethink STT-RAM based memory designs by emphasizing its probabilistic retention property.