The Experts below are selected from a list of 318 Experts worldwide ranked by ideXlab platform

Dian Zhou - One of the best experts on this subject based on the ideXlab platform.

  • Frequency domain wavelet method for High-Speed Circuit simulation
    2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353), 2002
    Co-Authors: Xuan Zeng, Sheng Huang, Jian Wang, Dian Zhou
    Abstract:

    In this paper, a Frequency domain Fast Wavelet Collocation Method (FFWCM) is proposed for the simulation of High-Speed linear VLSI Circuits. Compared with the time domain Fast Wavelet Collocation Method, the proposed FFWCM solves the state equation in the frequency domain and reduces the problem unknowns by avoiding expanding all the state variables with wavelet functions. Moreover, frequency domain singularities can be easily handled by an efficient adaptive scheme and the simulation error bound is guaranteed in the frequency domain. As a result, memory space and simulation time are greatly reduced by FFWCM, which makes it efficient for simulating large scale Circuits. Numerical experimental results have further demonstrated the promising features of FFWCM.

  • A frequency domain fast wavelet collocation method for High-Speed Circuit simulation
    ASICON 2001. 2001 4th International Conference on ASIC Proceedings (Cat. No.01TH8549), 2001
    Co-Authors: Xuan Zeng, Sheng Huang, Jian Wang, Dian Zhou
    Abstract:

    In this paper, we present the frequency domain fast wavelet collocation method (FFWCM) for High-Speed VLSI Circuit simulation. Compared with the time domain fast wavelet collocation method (TFWCM), FFWCM presents the following merits. First, it consumes much less memory space and computation time, and can effectively deal with large scale Circuits. Second, the frequency domain singularity can be easily handled by adaptive schemes and a frequency domain uniform error distribution can be achieved. Furthermore, the approximated time domain analytical solution can be simply obtained without performing the time consuming numeric inverse Laplace transforms. Numerical experimental results have further demonstrated the promising features of FFWCM.

  • A fast wavelet collocation method for High-Speed Circuit simulation
    IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 1999
    Co-Authors: Dian Zhou
    Abstract:

    The advance of very large scale integration (VLSI) systems has been continuously challenging today's Circuit simulators in both computational Speed and stability. This paper presents a novel approach, the fast wavelet collocation method (FWCM), for High-Speed Circuit simulation. FWCM has the following properties: (1) it works in the time domain, so that Circuit nonlinearity can be handled and numerical accuracy can be well controlled, unlike the method of working in the frequency domain where numerical error may become uncontrolled during the inverse Laplace transform; (2) the wavelet property of localization in both the time and frequency domains makes a uniform approximation possible, which is generally not found in time-marching methods; (3) it is very effective in treating singularities which often develop in High-Speed ICs; (4) an adaptive scheme exists; and (5) it has an O(h/sup 4/) convergence rate, where h is the step length. Numerical experiments further demonstrated the promising features of FWCM in High-Speed IC simulation.

T. Shiba - One of the best experts on this subject based on the ideXlab platform.

  • A CMOS-compatible rapid vapor-phase doping process for CMOS scaling
    IEEE Transactions on Electron Devices, 2004
    Co-Authors: T. Uchino, P. Ashburn, Y. Kiyota, T. Shiba
    Abstract:

    An advanced CMOS process, which used rapid vapor-phase doping (RVD) for pMOSFETs and solid-phase diffusion (SPD) for nMOSFETs, has been developed. Using the RVD technique, a 40-nm-deep p-type extension with a sheet resistance as low as 400 /spl Omega//sq has been realized. These RVD and SPD devices demonstrate excellent short-channel characteristics down to 0.1 /spl mu/m channel length and 40% Higher drain current, compared with conventional devices with ion implanted source/drain (S/D) extensions, and High-Speed Circuit performance. We investigate the effect of the S/D extension structure on the device performance and find that a gate extension overlap of 25 nm enables excellent dc and High-Speed Circuit performance in 0.1-/spl mu/m devices.

  • 0.1 /spl mu/m CMOS with shallow and steep source/drain extensions fabricated by using rapid vapor-phase doping (RVD)
    1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325), 1999
    Co-Authors: T. Uchino, Y. Kiyota, T. Shiba
    Abstract:

    We have developed an advanced 0.1 /spl mu/m CMOS technology to form 39 nm deep p-type junctions with sheet resistance as low as 630 /spl Omega//sq using two techniques in combination: rapid vapor-phase doping (RVD) and solid-phase diffusion (SPD). These RVD- and SPD-devices have shown excellent short channel characteristics down to 0.1 /spl mu/m effective channel length and 40% Higher maximum drain current compared with conventional devices with ion implanted source/drain extensions (SDEs), and High-Speed Circuit performance. We have also investigated the effect of the SDE structure on device performance. We found that a gate-extension overlap of 0.05 /spl mu/m enabled excellent DC and High-Speed Circuit performance in 0.1-/spl mu/m devices.

Byung-sik Moon - One of the best experts on this subject based on the ideXlab platform.

  • Low-voltage, High-Speed Circuit designs for gigabit DRAMs
    IEEE Journal of Solid-State Circuits, 1997
    Co-Authors: Byung-sik Moon, Hongil Yoon
    Abstract:

    This paper describes several new Circuit design techniques for low V/sub CC/ regions: 1) a charge-amplifying boosted sensing (CABS) scheme which amplifies the sensing voltage difference (/spl Delta/V/sub BL/) as well as the V/sub GS/ margin by boosting the sensing node voltage with a voltage dependent boosting capacitor and 2) an I/O current sense amplifier with a High gain using a cross-coupled current mirror control scheme and reduced temperature sensitivity using a simple temperature-compensation scheme. An experimental 16 Mb DRAM chip with the 0.18-/spl mu/m twin-well, triple-metal CMOS process has been fabricated, and an access time from the row address strobe (t/sub RAC/) of 28 ns at V/sub cc/=1.5 V and T=25/spl deg/C has been obtained.

  • Low voltage High Speed Circuit designs for giga-bit DRAMs
    1996 Symposium on VLSI Circuits. Digest of Technical Papers, 1996
    Co-Authors: Byung-sik Moon
    Abstract:

    An experimental 16 Mb DRAM for giga scale densities with a charge-amplifying boosted sensing (CABS) scheme and a new I/O large gain current sense amplifier using a cross-coupled current mirror control scheme achieves a t/sub RAC/ of 28 ns and an average operating current of 22 mA at V/sub CC/=1.5 V, t/sub RC/=70 ns, T=25/spl deg/C. This chip has been fabricated using a 0.18 /spl mu/m twin-well CMOS process with KrF lithography having transistor channel lengths of 0.32(n)/0.40(p)/spl mu/m and low resistance TiSi/sub 2/ wordlines.

Pedram Mohseni - One of the best experts on this subject based on the ideXlab platform.

  • A High-Speed Circuit architecture for IR-UWB transmission of fast-scan cyclic voltammetry in 0.35 εm CMOS
    Conference proceedings : ... Annual International Conference of the IEEE Engineering in Medicine and Biology Society. IEEE Engineering in Medicine and, 2010
    Co-Authors: Hamidreza Zamani, Pedram Mohseni
    Abstract:

    This paper reports on the design of a High-Speed Circuit for impulse radio ultra-wideband (IR-UWB) transmission of 16-channel neurochemical activity recorded using 300-V/s fast-scan cyclic voltammetry (FSCV). Simulated in a low-cost 0.35-em standard complementary metal-oxide-semiconductor (CMOS) technology, the Circuit generates 3rd-derivative Gaussian pulses with sub-nanosecond duration, which are Highpass filtered externally using a 4th-order Butterworth filter before feeding to an off-chip UWB antenna. The power spectral density (PSD) achieves a peak emission frequency of 4.6 GHz with a 2.3-GHz bandwidth (-10 dB), and is fully compliant with the UWB emission mask. The energy efficiency in pulse generation is 161.7 pJ/pulse that leads to a power consumption of 4.85 mW from 3.3 V for a data rate of 15 Mbps, when two pulses are used to transmit a single data bit.

  • A High-Speed Circuit architecture for IR-UWB transmission of fast-scan cyclic voltammetry in 0.35 εm CMOS
    2010 Annual International Conference of the IEEE Engineering in Medicine and Biology, 2010
    Co-Authors: Hamidreza Zamani, Pedram Mohseni
    Abstract:

    This paper reports on the design of a High-Speed Circuit for impulse radio ultra-wideband (IR-UWB) transmission of 16-channel neurochemical activity recorded using 300-V/s fast-scan cyclic voltammetry (FSCV). Simulated in a low-cost 0.35-μm standard complementary metal-oxide-semiconductor (CMOS) technology, the Circuit generates 3rd-derivative Gaussian pulses with sub-nanosecond duration, which are Highpass filtered externally using a 4th-order Butterworth filter before feeding to an off-chip UWB antenna. The power spectral density (PSD) achieves a peak emission frequency of 4.6 GHz with a 2.3-GHz bandwidth (-10 dB), and is fully compliant with the UWB emission mask. The energy efficiency in pulse generation is 161.7 pJ/pulse that leads to a power consumption of 4.85 mW from 3.3 V for a data rate of 15 Mbps, when two pulses are used to transmit a single data bit.

T. Uchino - One of the best experts on this subject based on the ideXlab platform.

  • A CMOS-compatible rapid vapor-phase doping process for CMOS scaling
    IEEE Transactions on Electron Devices, 2004
    Co-Authors: T. Uchino, P. Ashburn, Y. Kiyota, T. Shiba
    Abstract:

    An advanced CMOS process, which used rapid vapor-phase doping (RVD) for pMOSFETs and solid-phase diffusion (SPD) for nMOSFETs, has been developed. Using the RVD technique, a 40-nm-deep p-type extension with a sheet resistance as low as 400 /spl Omega//sq has been realized. These RVD and SPD devices demonstrate excellent short-channel characteristics down to 0.1 /spl mu/m channel length and 40% Higher drain current, compared with conventional devices with ion implanted source/drain (S/D) extensions, and High-Speed Circuit performance. We investigate the effect of the S/D extension structure on the device performance and find that a gate extension overlap of 25 nm enables excellent dc and High-Speed Circuit performance in 0.1-/spl mu/m devices.

  • 0.1 /spl mu/m CMOS with shallow and steep source/drain extensions fabricated by using rapid vapor-phase doping (RVD)
    1999 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.99CH36325), 1999
    Co-Authors: T. Uchino, Y. Kiyota, T. Shiba
    Abstract:

    We have developed an advanced 0.1 /spl mu/m CMOS technology to form 39 nm deep p-type junctions with sheet resistance as low as 630 /spl Omega//sq using two techniques in combination: rapid vapor-phase doping (RVD) and solid-phase diffusion (SPD). These RVD- and SPD-devices have shown excellent short channel characteristics down to 0.1 /spl mu/m effective channel length and 40% Higher maximum drain current compared with conventional devices with ion implanted source/drain extensions (SDEs), and High-Speed Circuit performance. We have also investigated the effect of the SDE structure on device performance. We found that a gate-extension overlap of 0.05 /spl mu/m enabled excellent DC and High-Speed Circuit performance in 0.1-/spl mu/m devices.