The Experts below are selected from a list of 318 Experts worldwide ranked by ideXlab platform

Daniel D. Gajski - One of the best experts on this subject based on the ideXlab platform.

  • An ultra-fast instruction set simulator
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2002
    Co-Authors: Jianwen Zhu, Daniel D. Gajski
    Abstract:

    In this paper, we present new techniques which further improve the static compilation-based instruction set architecture (ISA) simulation by the aggressive utilization of the Host Machine resources. Such utilization is achieved by defining a low-level code-generation interface specialized for ISA simulation, rather than the traditional approaches which use C as a code-generation interface. We are able to perform the simulation at a speed of up to 10/sup 2/ millions of simulated instructions per second (MIPS) on a 270 MHz Ultra-5 workstation. This result is only on average 1.6 times slower than the native execution on the Host Machine, the fastest to the best of our knowledge.

  • A retargetable, ultra-fast instruction set simulator
    Proceedings of the conference on Design automation and test in Europe - DATE '99, 1999
    Co-Authors: Jianwen Zhu, Daniel D. Gajski
    Abstract:

    In this paper we present new techniques which further improve the static compiled instruction set architecture (ISA) simulation by the aggressive utilization of the Host Machine resources. Such utilization is achieved by defining a low level code generation interface specialized for ISA simulation, rather than the traditional approaches which use C as a code generation interface. We are able to perform the simulation at a speed up to 10/sup 2/ millions of simulated instructions per second (MIPS). This result is only 1.1-2.5 times slower than the native execution on the Host Machine, the fastest to the best of our knowledge. Furthermore, the code generation interface is organized to implement a RISC like virtual Machine, which makes our tool easily retargetable to many Host platforms.

Edwin H.-m. Sha - One of the best experts on this subject based on the ideXlab platform.

  • MASS - Reprogramming with Minimal Transferred Data on Wireless Sensor Network
    2009 IEEE 6th International Conference on Mobile Adhoc and Sensor Systems, 2009
    Co-Authors: Chun Jason Xue, Edwin H.-m. Sha
    Abstract:

    In Wireless Sensor Networks, the preloaded program code and data on sensor nodes often need to be updated due to changes in user requirements or environmental conditions. Sensor nodes are severely restricted by energy constraints. It is especially energy consuming for sensor nodes to update code through radio packages. To efficiently update code through wireless radio, we propose an algorithm, Reprogramming with Minimal Transferred Data (RMTD), to find the optimum combination of copying from the old code image and downloading from the Host Machine to minimize the number of bytes needed to be transferred from the Host Machine to a sensor node. Our experiments show that, for small code modifications, RMTD reduces the number of bytes transferred by 93.25% over the existing Rsync-based algorithm. For normal code changes, RMTD shows an improvement of 59.82% in average.

  • WASA - Minimizing Transferred Data for Code Update on Wireless Sensor Network
    Wireless Algorithms Systems and Applications, 2008
    Co-Authors: Chun Jason Xue, Meikang Qiu, Wei-che Tseng, Lei Zhang, Edwin H.-m. Sha
    Abstract:

    In Wireless Sensor Networks, the preloaded program code and data on sensor nodes often need to be updated due to changes in user requirements or environmental conditions. Sensor nodes are severely restricted by energy constraints. It is especially energy consuming for sensor nodes to update code through radio packages. To efficiently update code through radio, we propose an algorithm, Minimum Data trasferred by Copying and Downloading(MDCD), to find the optimum combination of copying from the old code image and downloading from the Host Machine to minimize the number of bytes needed to be transferred from the Host Machine to the sensor node. Our experiments show that, for small code modifications, MDCD reduces the number of bytes transferred by 92.77% over the existing Rsync-based algorithm. For normal code changes, MDCD shows an improvement of 46.03% in average.

Ashraf Salem - One of the best experts on this subject based on the ideXlab platform.

  • A new approach for interfacing SystemC-AMS models with hardware-emulated platforms
    2015 Tenth International Conference on Computer Engineering & Systems (ICCES), 2015
    Co-Authors: Hanan Tawfik, Mona Safar, Mohamed Abdelsalam, M. Watheq El-kharashi, Ashraf Salem
    Abstract:

    Since its introduction, SystemC-AMS extensions to SystemC have been used in several applications to model the analog part of a heterogeneous SoC. In this case, the SoC is usually a pure simulation model where the digital part is modeled using SystemC. If an emulation verification environment is used, the digital part of the SoC would be running on the emulator while the analog part, modeled with SystemC-AMS, would be running on the emulator Host Machine. In this paper, we propose an approach to interface SystemC-AMS models running on the emulator Host Machine with digital models running on the emulator. The interfacing challenge, addressed by this approach, lies in the fact that SystemC-AMS is a timed environment with a time wheel completely independent from the emulation time wheel. We also describe a case study that demonstrates the validity of the proposed approach.

  • IDT - Toward the interfacing of systemC-AMS models with hardware-emulated platforms
    2015 10th International Design & Test Symposium (IDT), 2015
    Co-Authors: Hanan Tawfik, Mona Safar, Mohamed Abdelsalam, M. Watheq El-kharashi, Ashraf Salem
    Abstract:

    Systems on chip (SoC) nowadays, have become heterogeneous in nature. They can be composed of a mix of analog and digital components. In some verification environments, SystemC models the digital components and SystemC-AMS extensions can be used to model the analog part. In an emulation environment, the digital components would be probably running on the emulator while the SystemC-AMS components would be running on the associated emulator Host Machine. In this paper, we propose an approach to interface those digital and analog components. This is challenging because SytemC-AMS is a timed environment with a time wheel completely decoupled from emulation time. We also propose a transaction packing technique that will minimize the communication overhead introduced due to frequent exchange of data between the components running on the emulator and the components running on the Host Machine. Finally, we describe a case study that illustrates the feasibility of the proposed interfacing approach.

Jianwen Zhu - One of the best experts on this subject based on the ideXlab platform.

  • An ultra-fast instruction set simulator
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2002
    Co-Authors: Jianwen Zhu, Daniel D. Gajski
    Abstract:

    In this paper, we present new techniques which further improve the static compilation-based instruction set architecture (ISA) simulation by the aggressive utilization of the Host Machine resources. Such utilization is achieved by defining a low-level code-generation interface specialized for ISA simulation, rather than the traditional approaches which use C as a code-generation interface. We are able to perform the simulation at a speed of up to 10/sup 2/ millions of simulated instructions per second (MIPS) on a 270 MHz Ultra-5 workstation. This result is only on average 1.6 times slower than the native execution on the Host Machine, the fastest to the best of our knowledge.

  • A retargetable, ultra-fast instruction set simulator
    Proceedings of the conference on Design automation and test in Europe - DATE '99, 1999
    Co-Authors: Jianwen Zhu, Daniel D. Gajski
    Abstract:

    In this paper we present new techniques which further improve the static compiled instruction set architecture (ISA) simulation by the aggressive utilization of the Host Machine resources. Such utilization is achieved by defining a low level code generation interface specialized for ISA simulation, rather than the traditional approaches which use C as a code generation interface. We are able to perform the simulation at a speed up to 10/sup 2/ millions of simulated instructions per second (MIPS). This result is only 1.1-2.5 times slower than the native execution on the Host Machine, the fastest to the best of our knowledge. Furthermore, the code generation interface is organized to implement a RISC like virtual Machine, which makes our tool easily retargetable to many Host platforms.

Chun Jason Xue - One of the best experts on this subject based on the ideXlab platform.

  • MASS - Reprogramming with Minimal Transferred Data on Wireless Sensor Network
    2009 IEEE 6th International Conference on Mobile Adhoc and Sensor Systems, 2009
    Co-Authors: Chun Jason Xue, Edwin H.-m. Sha
    Abstract:

    In Wireless Sensor Networks, the preloaded program code and data on sensor nodes often need to be updated due to changes in user requirements or environmental conditions. Sensor nodes are severely restricted by energy constraints. It is especially energy consuming for sensor nodes to update code through radio packages. To efficiently update code through wireless radio, we propose an algorithm, Reprogramming with Minimal Transferred Data (RMTD), to find the optimum combination of copying from the old code image and downloading from the Host Machine to minimize the number of bytes needed to be transferred from the Host Machine to a sensor node. Our experiments show that, for small code modifications, RMTD reduces the number of bytes transferred by 93.25% over the existing Rsync-based algorithm. For normal code changes, RMTD shows an improvement of 59.82% in average.

  • WASA - Minimizing Transferred Data for Code Update on Wireless Sensor Network
    Wireless Algorithms Systems and Applications, 2008
    Co-Authors: Chun Jason Xue, Meikang Qiu, Wei-che Tseng, Lei Zhang, Edwin H.-m. Sha
    Abstract:

    In Wireless Sensor Networks, the preloaded program code and data on sensor nodes often need to be updated due to changes in user requirements or environmental conditions. Sensor nodes are severely restricted by energy constraints. It is especially energy consuming for sensor nodes to update code through radio packages. To efficiently update code through radio, we propose an algorithm, Minimum Data trasferred by Copying and Downloading(MDCD), to find the optimum combination of copying from the old code image and downloading from the Host Machine to minimize the number of bytes needed to be transferred from the Host Machine to the sensor node. Our experiments show that, for small code modifications, MDCD reduces the number of bytes transferred by 92.77% over the existing Rsync-based algorithm. For normal code changes, MDCD shows an improvement of 46.03% in average.