The Experts below are selected from a list of 187026 Experts worldwide ranked by ideXlab platform
Massimo Poncino - One of the best experts on this subject based on the ideXlab platform.
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Dynamic Management of Thermally-Induced Clock Skew : An Implementation Perspective
Lecture Notes in Computer Science, 2006Co-Authors: Abhishek Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, Alberto Macii, Enrico Macii, Massimo PoncinoAbstract:High performance VLSI designs require strict control over clock skew since skew directly impacts the cycle time calculation. For nano-meter CMOS designs, clock-skew and signal integrity are tremendously affected by process and temperature variations. A successful high performance VLSI design should not only aim to minimize the clock skew, but also control it while the chip is running. The issues rising out of temperature variations are particularly tough to tackle because of its dynamic, run-time nature. Although techniques for clock skew management/tuning due to temperature do exist in literature, they have mainly focused on how to solve skew issues, and have usually regarded the Implementation of the thermal management scheme as a secondary problem. In this work we focus on the Implementation issues involved in the Implementation of a thermal management unit (TMU) relative to a skew management scheme based on the insertion of variable delay buffers (VDBs). We demonstrate the feasibility of the VDB-based methodology and compare different Implementation styles, showing that the most efficient TMU can he implemented with negligible overhead in various physical level metrics (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37%. in via-number).
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PATMOS - Dynamic management of thermally-induced clock skew: an Implementation Perspective
Lecture Notes in Computer Science, 2006Co-Authors: Abhishek Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, Alberto Macii, Enrico Macii, Massimo PoncinoAbstract:High performance VLSI designs require strict control over clock skew since skew directly impacts the cycle time calculation. For nano-meter CMOS designs, clock-skew and signal integrity are tremendously affected by process and temperature variations. A successful high performance VLSI design should not only aim to minimize the clock skew, but also control it while the chip is running. The issues rising out of temperature variations are particularly tough to tackle because of its dynamic, run-time nature. Although techniques for clock skew management/tuning due to temperature do exist in literature, they have mainly focused on how to solve skew issues, and have usually regarded the Implementation of the thermal management scheme as a secondary problem. In this work we focus on the Implementation issues involved in the Implementation of a thermal management unit (TMU) relative to a skew management scheme based on the insertion of variable delay buffers (VDBs). We demonstrate the feasibility of the VDB-based methodology, and compare different Implementation styles, showing that the most efficient TMU can be implemented with negligible overhead in various physical level metrics (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37% in via-number).
Abhishek Chakraborty - One of the best experts on this subject based on the ideXlab platform.
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Dynamic Management of Thermally-Induced Clock Skew : An Implementation Perspective
Lecture Notes in Computer Science, 2006Co-Authors: Abhishek Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, Alberto Macii, Enrico Macii, Massimo PoncinoAbstract:High performance VLSI designs require strict control over clock skew since skew directly impacts the cycle time calculation. For nano-meter CMOS designs, clock-skew and signal integrity are tremendously affected by process and temperature variations. A successful high performance VLSI design should not only aim to minimize the clock skew, but also control it while the chip is running. The issues rising out of temperature variations are particularly tough to tackle because of its dynamic, run-time nature. Although techniques for clock skew management/tuning due to temperature do exist in literature, they have mainly focused on how to solve skew issues, and have usually regarded the Implementation of the thermal management scheme as a secondary problem. In this work we focus on the Implementation issues involved in the Implementation of a thermal management unit (TMU) relative to a skew management scheme based on the insertion of variable delay buffers (VDBs). We demonstrate the feasibility of the VDB-based methodology and compare different Implementation styles, showing that the most efficient TMU can he implemented with negligible overhead in various physical level metrics (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37%. in via-number).
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PATMOS - Dynamic management of thermally-induced clock skew: an Implementation Perspective
Lecture Notes in Computer Science, 2006Co-Authors: Abhishek Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, Alberto Macii, Enrico Macii, Massimo PoncinoAbstract:High performance VLSI designs require strict control over clock skew since skew directly impacts the cycle time calculation. For nano-meter CMOS designs, clock-skew and signal integrity are tremendously affected by process and temperature variations. A successful high performance VLSI design should not only aim to minimize the clock skew, but also control it while the chip is running. The issues rising out of temperature variations are particularly tough to tackle because of its dynamic, run-time nature. Although techniques for clock skew management/tuning due to temperature do exist in literature, they have mainly focused on how to solve skew issues, and have usually regarded the Implementation of the thermal management scheme as a secondary problem. In this work we focus on the Implementation issues involved in the Implementation of a thermal management unit (TMU) relative to a skew management scheme based on the insertion of variable delay buffers (VDBs). We demonstrate the feasibility of the VDB-based methodology, and compare different Implementation styles, showing that the most efficient TMU can be implemented with negligible overhead in various physical level metrics (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37% in via-number).
P. Sithambaram - One of the best experts on this subject based on the ideXlab platform.
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Dynamic Management of Thermally-Induced Clock Skew : An Implementation Perspective
Lecture Notes in Computer Science, 2006Co-Authors: Abhishek Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, Alberto Macii, Enrico Macii, Massimo PoncinoAbstract:High performance VLSI designs require strict control over clock skew since skew directly impacts the cycle time calculation. For nano-meter CMOS designs, clock-skew and signal integrity are tremendously affected by process and temperature variations. A successful high performance VLSI design should not only aim to minimize the clock skew, but also control it while the chip is running. The issues rising out of temperature variations are particularly tough to tackle because of its dynamic, run-time nature. Although techniques for clock skew management/tuning due to temperature do exist in literature, they have mainly focused on how to solve skew issues, and have usually regarded the Implementation of the thermal management scheme as a secondary problem. In this work we focus on the Implementation issues involved in the Implementation of a thermal management unit (TMU) relative to a skew management scheme based on the insertion of variable delay buffers (VDBs). We demonstrate the feasibility of the VDB-based methodology and compare different Implementation styles, showing that the most efficient TMU can he implemented with negligible overhead in various physical level metrics (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37%. in via-number).
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PATMOS - Dynamic management of thermally-induced clock skew: an Implementation Perspective
Lecture Notes in Computer Science, 2006Co-Authors: Abhishek Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, Alberto Macii, Enrico Macii, Massimo PoncinoAbstract:High performance VLSI designs require strict control over clock skew since skew directly impacts the cycle time calculation. For nano-meter CMOS designs, clock-skew and signal integrity are tremendously affected by process and temperature variations. A successful high performance VLSI design should not only aim to minimize the clock skew, but also control it while the chip is running. The issues rising out of temperature variations are particularly tough to tackle because of its dynamic, run-time nature. Although techniques for clock skew management/tuning due to temperature do exist in literature, they have mainly focused on how to solve skew issues, and have usually regarded the Implementation of the thermal management scheme as a secondary problem. In this work we focus on the Implementation issues involved in the Implementation of a thermal management unit (TMU) relative to a skew management scheme based on the insertion of variable delay buffers (VDBs). We demonstrate the feasibility of the VDB-based methodology, and compare different Implementation styles, showing that the most efficient TMU can be implemented with negligible overhead in various physical level metrics (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37% in via-number).
A. Sathanur - One of the best experts on this subject based on the ideXlab platform.
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Dynamic Management of Thermally-Induced Clock Skew : An Implementation Perspective
Lecture Notes in Computer Science, 2006Co-Authors: Abhishek Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, Alberto Macii, Enrico Macii, Massimo PoncinoAbstract:High performance VLSI designs require strict control over clock skew since skew directly impacts the cycle time calculation. For nano-meter CMOS designs, clock-skew and signal integrity are tremendously affected by process and temperature variations. A successful high performance VLSI design should not only aim to minimize the clock skew, but also control it while the chip is running. The issues rising out of temperature variations are particularly tough to tackle because of its dynamic, run-time nature. Although techniques for clock skew management/tuning due to temperature do exist in literature, they have mainly focused on how to solve skew issues, and have usually regarded the Implementation of the thermal management scheme as a secondary problem. In this work we focus on the Implementation issues involved in the Implementation of a thermal management unit (TMU) relative to a skew management scheme based on the insertion of variable delay buffers (VDBs). We demonstrate the feasibility of the VDB-based methodology and compare different Implementation styles, showing that the most efficient TMU can he implemented with negligible overhead in various physical level metrics (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37%. in via-number).
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PATMOS - Dynamic management of thermally-induced clock skew: an Implementation Perspective
Lecture Notes in Computer Science, 2006Co-Authors: Abhishek Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, Alberto Macii, Enrico Macii, Massimo PoncinoAbstract:High performance VLSI designs require strict control over clock skew since skew directly impacts the cycle time calculation. For nano-meter CMOS designs, clock-skew and signal integrity are tremendously affected by process and temperature variations. A successful high performance VLSI design should not only aim to minimize the clock skew, but also control it while the chip is running. The issues rising out of temperature variations are particularly tough to tackle because of its dynamic, run-time nature. Although techniques for clock skew management/tuning due to temperature do exist in literature, they have mainly focused on how to solve skew issues, and have usually regarded the Implementation of the thermal management scheme as a secondary problem. In this work we focus on the Implementation issues involved in the Implementation of a thermal management unit (TMU) relative to a skew management scheme based on the insertion of variable delay buffers (VDBs). We demonstrate the feasibility of the VDB-based methodology, and compare different Implementation styles, showing that the most efficient TMU can be implemented with negligible overhead in various physical level metrics (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37% in via-number).
K. Duraisami - One of the best experts on this subject based on the ideXlab platform.
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Dynamic Management of Thermally-Induced Clock Skew : An Implementation Perspective
Lecture Notes in Computer Science, 2006Co-Authors: Abhishek Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, Alberto Macii, Enrico Macii, Massimo PoncinoAbstract:High performance VLSI designs require strict control over clock skew since skew directly impacts the cycle time calculation. For nano-meter CMOS designs, clock-skew and signal integrity are tremendously affected by process and temperature variations. A successful high performance VLSI design should not only aim to minimize the clock skew, but also control it while the chip is running. The issues rising out of temperature variations are particularly tough to tackle because of its dynamic, run-time nature. Although techniques for clock skew management/tuning due to temperature do exist in literature, they have mainly focused on how to solve skew issues, and have usually regarded the Implementation of the thermal management scheme as a secondary problem. In this work we focus on the Implementation issues involved in the Implementation of a thermal management unit (TMU) relative to a skew management scheme based on the insertion of variable delay buffers (VDBs). We demonstrate the feasibility of the VDB-based methodology and compare different Implementation styles, showing that the most efficient TMU can he implemented with negligible overhead in various physical level metrics (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37%. in via-number).
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PATMOS - Dynamic management of thermally-induced clock skew: an Implementation Perspective
Lecture Notes in Computer Science, 2006Co-Authors: Abhishek Chakraborty, K. Duraisami, A. Sathanur, P. Sithambaram, Alberto Macii, Enrico Macii, Massimo PoncinoAbstract:High performance VLSI designs require strict control over clock skew since skew directly impacts the cycle time calculation. For nano-meter CMOS designs, clock-skew and signal integrity are tremendously affected by process and temperature variations. A successful high performance VLSI design should not only aim to minimize the clock skew, but also control it while the chip is running. The issues rising out of temperature variations are particularly tough to tackle because of its dynamic, run-time nature. Although techniques for clock skew management/tuning due to temperature do exist in literature, they have mainly focused on how to solve skew issues, and have usually regarded the Implementation of the thermal management scheme as a secondary problem. In this work we focus on the Implementation issues involved in the Implementation of a thermal management unit (TMU) relative to a skew management scheme based on the insertion of variable delay buffers (VDBs). We demonstrate the feasibility of the VDB-based methodology, and compare different Implementation styles, showing that the most efficient TMU can be implemented with negligible overhead in various physical level metrics (0.67% in area, 0.62% in wire-length, 0.33% in power, and 0.37% in via-number).
