The Experts below are selected from a list of 72 Experts worldwide ranked by ideXlab platform

D.g. Saab - One of the best experts on this subject based on the ideXlab platform.

Wang Zhong - One of the best experts on this subject based on the ideXlab platform.

Giovanni Squillero - One of the best experts on this subject based on the ideXlab platform.

  • Asian Test Symposium - A genetic algorithm for the computation of Initialization Sequences for synchronous sequential circuits
    Proceedings Sixth Asian Test Symposium (ATS'97), 1997
    Co-Authors: Fulvio Corno, Maurizio Rebaudengo, Paolo Prinetto, M. Sonza Reorda, Giovanni Squillero
    Abstract:

    Testing circuits which do not include a global reset signal requires either complex ATPG algorithms based on 9- or even 256-valued algebras, or some suitable method to generate Initialization Sequences. This paper follows the latter approach, and presents a new method to the automated generation of an Initialization Sequence for synchronous sequential circuits. We propose a Genetic Algorithm providing a Sequence that aims at initializing the highest number of flip flops with the lowest number of vectors. The experimental results show that the approach is feasible to be applied even to the largest benchmark circuits and that it compares well to other known approaches in terms of initialized flip flops and Sequence length. Finally, this paper shows how the Initialization Sequences can be fruitfully exploited by simplifying the ATPG process.

  • ICCD - A new approach for Initialization Sequences computation for synchronous sequential circuits
    Proceedings International Conference on Computer Design VLSI in Computers and Processors, 1997
    Co-Authors: Fulvio Corno, Maurizio Rebaudengo, Paolo Prinetto, M. Sonza Reorda, Giovanni Squillero
    Abstract:

    This paper presents a new approach to the automated generation of an Initialization Sequence for synchronous sequential circuits. Finding an Initialization Sequence is a hard task when a global reset signal is not available, and functional techniques often cannot handle large circuits. We propose a Genetic Algorithm providing a Sequence that aims at initializing the highest number of flip flops with the lowest number of vectors. The experimental results we provide shore that the approach is feasible to be applied even to the largest benchmark circuits and that it compares well to other known approaches in terms of initialized flip flops and Sequence length.

Srimat T Chakradhar - One of the best experts on this subject based on the ideXlab platform.

  • Initialization issues in asynchronous circuit synthesis
    Journal of Electronic Testing, 1996
    Co-Authors: Savita Banerjee, Rabindra K. Roy, Srimat T Chakradhar
    Abstract:

    A design specification is said to be functionally uninitializable if an initializable implementation cannot be obtained. Due to the absence of any Initialization Sequence, a fault simulator or test generator that assumes an unknown starting state will be completely ineffective for uninitializable circuits. We present a novel procedure for synthesizing initializable asynchronous circuits from functionally uninitializable Signal Transition Graphs (STG). After characterizing the necessary conditions for functional uninitializability, we propose a technique that transforms the original STG into an equivalent, functionally initializable STG. We show that the presence of concurrency provides the designer with an extra degree of flexibility when implementing the circuit. It is shown that initializability can be achieved by sacrificing minimal concurrency and without violating the syntactic properties of the STG required for a hazard-free implementation. The synthesis of a trigger module illustrates this procedure.

  • Synthesis of initializable asynchronous circuits
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1996
    Co-Authors: Srimat T Chakradhar, Rabindra K. Roy, Savita Banerjee, Dinesh Kumar Pradhan
    Abstract:

    We show that existing synthesis techniques may produce asynchronous circuits that are not initializable by gate level analysis tools even when the design is functionally initializable. Due to the absence of any Initialization Sequence, a fault simulator or test generator that assumes an unknown starting state will be completely ineffective for these circuits. In this paper, we show that proper consideration of initializability during the asynchronous circuit synthesis procedure can guarantee initializable implementations. We show that the assignment of don't cares during the synthesis procedure affects the initializability of the final implementation. We present a novel implicit enumeration procedure that selectively assigns don't cares to obtain an initializable implementation. Initialization Sequences are obtained as a by-product of our synthesis procedure

  • VLSI Design - Synthesis of initializable asynchronous circuits
    Proceedings of 7th International Conference on VLSI Design, 1
    Co-Authors: Srimat T Chakradhar, Rabindra K. Roy, Savita Banerjee, Dinesh Kumar Pradhan
    Abstract:

    We show that existing synthesis techniques may produce asynchronous circuits that are not initializable by gate level analysis tools even when the design is functionally initializable. Due to the absence of any Initialization Sequence, a fault simulator or test generator that assumes an unknown starting state will be completely ineffective for these circuits. In this paper, we show that proper consideration of initializability during the asynchronous circuit synthesis procedure can guarantee initializable implementations, The assignment of don't cares during the synthesis procedure is intimately related to the initializability of the final implementation. We present a novel implicit enumeration procedure that selectively assigns don't cares to obtain an initializable implementation. Initialization Sequences are obtained as a by product of our synthesis procedure. >

Dinesh Kumar Pradhan - One of the best experts on this subject based on the ideXlab platform.

  • Synthesis of initializable asynchronous circuits
    IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 1996
    Co-Authors: Srimat T Chakradhar, Rabindra K. Roy, Savita Banerjee, Dinesh Kumar Pradhan
    Abstract:

    We show that existing synthesis techniques may produce asynchronous circuits that are not initializable by gate level analysis tools even when the design is functionally initializable. Due to the absence of any Initialization Sequence, a fault simulator or test generator that assumes an unknown starting state will be completely ineffective for these circuits. In this paper, we show that proper consideration of initializability during the asynchronous circuit synthesis procedure can guarantee initializable implementations. We show that the assignment of don't cares during the synthesis procedure affects the initializability of the final implementation. We present a novel implicit enumeration procedure that selectively assigns don't cares to obtain an initializable implementation. Initialization Sequences are obtained as a by-product of our synthesis procedure

  • VLSI Design - Synthesis of initializable asynchronous circuits
    Proceedings of 7th International Conference on VLSI Design, 1
    Co-Authors: Srimat T Chakradhar, Rabindra K. Roy, Savita Banerjee, Dinesh Kumar Pradhan
    Abstract:

    We show that existing synthesis techniques may produce asynchronous circuits that are not initializable by gate level analysis tools even when the design is functionally initializable. Due to the absence of any Initialization Sequence, a fault simulator or test generator that assumes an unknown starting state will be completely ineffective for these circuits. In this paper, we show that proper consideration of initializability during the asynchronous circuit synthesis procedure can guarantee initializable implementations, The assignment of don't cares during the synthesis procedure is intimately related to the initializability of the final implementation. We present a novel implicit enumeration procedure that selectively assigns don't cares to obtain an initializable implementation. Initialization Sequences are obtained as a by product of our synthesis procedure. >