The Experts below are selected from a list of 10881 Experts worldwide ranked by ideXlab platform
J.h. Patel - One of the best experts on this subject based on the ideXlab platform.
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fast static compaction algorithms for Sequential Circuit test vectors
IEEE Transactions on Computers, 1999Co-Authors: Michael S. Hsiao, E M Rudnick, J.h. PatelAbstract:Two fast algorithms for static test sequence compaction are proposed for Sequential Circuits. The algorithms are based on the observation that test sequences traverse through a small set of states and some states are frequently revisited throughout the application of a test set. Subsequences that start and end on the same states may be removed if necessary and if sufficient conditions are met for them. Contrary to the previously proposed methods, where multitudes of fault simulations are required, the techniques described in this paper require only two fault simulation passes and are applied to test sequences generated by various test generators, resulting in significant compactions very quickly for Circuits that have many revisited states.
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fast algorithms for static compaction of Sequential Circuit test vectors
VLSI Test Symposium, 1997Co-Authors: M S Nsiao, E M Rudnick, J.h. PatelAbstract:Two fast algorithms for static test sequence compaction are proposed for Sequential Circuits. The algorithms are based on the observation that test sequences traverse through a small set of states, and some states are frequently re-visited throughout the application of a test set. Subsequences that start and end on the same states may be removed if necessary and sufficient conditions are met for them. The techniques require only two fault simulation passes and are applied to test sequences generated by various test generators, resulting in significant compactions very quickly for Circuits that have many revisited states.
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Sequential Circuit test generation using dynamic state traversal
European Design and Test Conference, 1997Co-Authors: Michael S. Hsiao, E.m. Rudnick, J.h. PatelAbstract:This research was supported in part by the Semiconductor Research Corporation under contract SRC 96-DP-109, in part by ARPA under contract DABT63-95-C-0069, and by Hewlett-Packard under an equipment grant. A new method for state justification is proposed for Sequential Circuit test generation. The linear list of states dynamically obtained during the derivation of test vectors is used to guide the search during state justification. State-transfer sequences may already be known that drive the Circuit from the current state to the target state. Otherwise, genetic engineering of existing state-transfer sequences is required. In both cases, genetic-algorithm-based techniques are used to generate valid state justification sequences for the Circuit in the presence of the target fault. This approach achieves extremely high fault coverages and thus outperforms previous deterministic and simulation-based techniques.
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combining deterministic and genetic approaches for Sequential Circuit test generation
Design Automation Conference, 1995Co-Authors: E.m. Rudnick, J.h. PatelAbstract:A hybrid Sequential Circuit test generator is described which combines deterministic algorithms for fault excitation and propagation with genetic algorithms for state justification. Deterministic procedures for state justification are used if the genetic approach is unsuccessful, to allow for identification of untestable faults and to improve the fault coverage. High fault coverages were obtained for the ISCAS89 benchmark Circuits and several additional Circuits, and in many cases the results are better than those for purely deterministic approaches.
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Sequential Circuit test generation in a genetic algorithm framework
Design Automation Conference, 1994Co-Authors: E.m. Rudnick, Gary S Greenstein, J.h. Patel, Thomas M NiermannAbstract:Test generation using deterministic fault-oriented algorithms is highly complex and time-consuming. New approaches are needed to augment the existing techniques, both to reduce execution time and to improve fault coverage. In this work, we describe a genetic algorithm (GA) framework for Sequential Circuit test generation. The GA evolves candidate test vectors and sequences, using a fault simulator to compute the fitness of each candidate test. Various GA parameters are studied, including alphabet size, fitness function, generation gap, population size, and mutation rate, as well as selection and crossover schemes. High fault coverages were obtained for most of the ISCAS89 Sequential benchmark Circuits, and execution times were significantly lower than in a deterministic test generator in most cases.
Srinivas Devadas - One of the best experts on this subject based on the ideXlab platform.
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Power Estimation Under User-Specified Input Sequences and Programs
Integrated Computer-Aided Engineering, 1998Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:We describe an approach to estimate the average power dissipation in Sequential logic Circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or processor is running specific application programs. Current approaches to Sequential Circuit power estimation are limited by the fact that the input sequences to the Sequential Circuit are assumed to be uncorrelated. In reality, the inputs come from other Sequential Circuits, or are application programs. In this paper we show how user-specified sequences and programs can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power estimation can be carried out using existing Sequential Circuit power estimation methods on a cascade Circuit consisting of the IMFSM and the original Sequential Circuit.
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techniques for the power estimation of Sequential logic Circuits under user specified input sequences and programs
International Symposium on Low Power Electronics and Design, 1995Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:We describe an approach to estimate the average power dissipation in Sequential logic Circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or processor is running specific application programs. Current approaches to Sequential Circuit power estimation are limited by the fact that the input sequences to the Sequential Circuit are assumed to be uncorrelated. In reality, the inputs come from other Sequential Circuits, or are application programs. In this paper we show how user-specified sequences and programs can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power estimation can be carried out using existing Sequential Circuit power estimation methods on a cascade Circuit consisting of the IMFSM and the original Sequential Circuit.
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ISLPD - Techniques for the power estimation of Sequential logic Circuits under user-specified input sequences and programs
Proceedings of the 1995 international symposium on Low power design - ISLPED '95, 1995Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:We describe an approach to estimate the average power dissipation in Sequential logic Circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or processor is running specific application programs. Current approaches to Sequential Circuit power estimation are limited by the fact that the input sequences to the Sequential Circuit are assumed to be uncorrelated. In reality, the inputs come from other Sequential Circuits, or are application programs. In this paper we show how user-specified sequences and programs can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power estimation can be carried out using existing Sequential Circuit power estimation methods on a cascade Circuit consisting of the IMFSM and the original Sequential Circuit.
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ICCAD - Retiming Sequential Circuits for low power
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1Co-Authors: Jose Monteiro, Srinivas Devadas, A. GhoshAbstract:Switching activity is the primary cause of power dissipation in CMOS combinational and Sequential Circuits. We give a method of estimating power in pipelined Sequential CMOS Circuits that accurately models the correlation between the vectors applied to the combinational logic of the Circuit. We explore the implications of the observation that the switching activity at flip-flop outputs in a synchronous Sequential Circuit can be significantly less than the activity at the flip-flop inputs. We present a retiming method that targets the power dissipation of a Sequential Circuit.
Jose Monteiro - One of the best experts on this subject based on the ideXlab platform.
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Power Estimation Under User-Specified Input Sequences and Programs
Integrated Computer-Aided Engineering, 1998Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:We describe an approach to estimate the average power dissipation in Sequential logic Circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or processor is running specific application programs. Current approaches to Sequential Circuit power estimation are limited by the fact that the input sequences to the Sequential Circuit are assumed to be uncorrelated. In reality, the inputs come from other Sequential Circuits, or are application programs. In this paper we show how user-specified sequences and programs can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power estimation can be carried out using existing Sequential Circuit power estimation methods on a cascade Circuit consisting of the IMFSM and the original Sequential Circuit.
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techniques for the power estimation of Sequential logic Circuits under user specified input sequences and programs
International Symposium on Low Power Electronics and Design, 1995Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:We describe an approach to estimate the average power dissipation in Sequential logic Circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or processor is running specific application programs. Current approaches to Sequential Circuit power estimation are limited by the fact that the input sequences to the Sequential Circuit are assumed to be uncorrelated. In reality, the inputs come from other Sequential Circuits, or are application programs. In this paper we show how user-specified sequences and programs can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power estimation can be carried out using existing Sequential Circuit power estimation methods on a cascade Circuit consisting of the IMFSM and the original Sequential Circuit.
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ISLPD - Techniques for the power estimation of Sequential logic Circuits under user-specified input sequences and programs
Proceedings of the 1995 international symposium on Low power design - ISLPED '95, 1995Co-Authors: Jose Monteiro, Srinivas DevadasAbstract:We describe an approach to estimate the average power dissipation in Sequential logic Circuits under user-specified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or processor is running specific application programs. Current approaches to Sequential Circuit power estimation are limited by the fact that the input sequences to the Sequential Circuit are assumed to be uncorrelated. In reality, the inputs come from other Sequential Circuits, or are application programs. In this paper we show how user-specified sequences and programs can be modeled using a finite state machine, termed an input-modeling finite state machines or IMFSM. Power estimation can be carried out using existing Sequential Circuit power estimation methods on a cascade Circuit consisting of the IMFSM and the original Sequential Circuit.
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ICCAD - Retiming Sequential Circuits for low power
Proceedings of 1993 International Conference on Computer Aided Design (ICCAD), 1Co-Authors: Jose Monteiro, Srinivas Devadas, A. GhoshAbstract:Switching activity is the primary cause of power dissipation in CMOS combinational and Sequential Circuits. We give a method of estimating power in pipelined Sequential CMOS Circuits that accurately models the correlation between the vectors applied to the combinational logic of the Circuit. We explore the implications of the observation that the switching activity at flip-flop outputs in a synchronous Sequential Circuit can be significantly less than the activity at the flip-flop inputs. We present a retiming method that targets the power dissipation of a Sequential Circuit.
Arlindo L Oliveira - One of the best experts on this subject based on the ideXlab platform.
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robust techniques for watermarking Sequential Circuit designs
Design Automation Conference, 1999Co-Authors: Arlindo L OliveiraAbstract:We present a methodology for the watermarking of synchronous Sequential Circuits that makes it possible to identify the authorship of designs by imposing a digital watermark on the state transition graph of the Circuit. The methodology is applicable to Sequential designs that are made available as firm Intellectual Property (IP), the designation commonly used to characterize designs specified as structural descriptions or Circuit netlists. The watermarking is obtained by manipulating the state transition graph of the design in such a way as to make it exhibit a chosen property that is extremely rare in non-watermarked Circuits, while, at the same time, not changing the functionality of the Circuit. This manipulation is performed without ever actually computing this graph in either implicit or explicit form. We present both theoretical and experimental results that show that the watermarking can be created and verified efficiently.
A Matrosova - One of the best experts on this subject based on the ideXlab platform.
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a fault tolerant Sequential Circuit design for soft errors based on fault secure Circuit
East-West Design and Test Symposium, 2016Co-Authors: S Ostanin, A Matrosova, N Butorina, V LavrovAbstract:This paper presents a fault-tolerant synchronous Sequential Circuit design based on fault-secure system with low overhead. The scheme has only one fault-secure Sequential Circuit, a normal (unprotected) Sequential Circuit, a checker and rather simple XOR Circuit. It is proved the reliability properties of the suggested scheme not only for single stuck-at faults at gate poles but for path delay faults transient and intermittent. It is supposed that each next fault appears when a previous one has disappeared.
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robdds application for finding the shortest transfer sequence of Sequential Circuit or only revealing existence of this sequence without deriving the sequence itself
East-West Design and Test Symposium, 2016Co-Authors: A Matrosova, V Andreeva, A MelnikovAbstract:Methods of revealing of transfer sequence existence of the length not more l for a set of states (internal states) without deriving the sequence itself and finding the shortest transfer sequence of the length not more l for a Sequential Circuit are developed. The methods are based on applying operations either on full ROBDDs, representing transition functions or fragments of these ROBDDs. Multiplications of the proper ROBDDs are executed with using full ROBDDs but summations — with using ROBDDs fragments. It is setup that for revealing transfer sequence existence we may use ROBDDs fragments depending on only state variables. When finding the shortest sequence we use ROBDDs so that each path originated by state variables has the only prolongation among input variables. The initial state of a Sequential Circuit is given. Set M0 of states one of which has to be reached is represented by the ROBDD.
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a fault tolerant Sequential Circuit design for safs and pdfs soft errors
International On-Line Testing Symposium, 2016Co-Authors: A Matrosova, S Ostanin, I Kirienko, E NikolaevaAbstract:This paper presents a fault-tolerant synchronous Sequential Circuit design based on self-checking system with low overhead. The scheme has a self-checking Sequential Circuit, a not self-testing checker and a normal (unprotected) Sequential Circuit. It is proved the reliability properties of the suggested scheme both for single stuck-at faults at gate poles and path delay faults transient and intermittent.
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Fully delay testable Sequential Circuits and problem of their structural minimization
2014 14th Biennial Baltic Electronic Conference (BEC), 2014Co-Authors: A Matrosova, E MitrofanovAbstract:The method of a Sequential Circuit design based on using a mixed description of a Circuit behavior is considered. A combinational part of a Sequential Circuit is examined. Its behavior is represented with a composition of ROBDD-graphs and monotonous products. The method provides fully delay testability of a combinational part of a Sequential Circuit. It is oriented to cut down the path lengths of the obtained Circuits. Experimental results are given that demonstrate advantages of the method. The possibilities of further structural minimization of the Circuits are discussed.
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delay testable Sequential Circuit designs
East-West Design and Test Symposium, 2013Co-Authors: A Matrosova, E Mitrofanov, Virendra SinghAbstract:New method of a Sequential Circuit design based on using mixed description of the Circuit behavior is suggested. A combinational part behavior of a Sequential Circuit is represented with the composition of ROBDDs (Reduced Ordered Binary Decision Diagrams) and monotonous products. The method provides fully delay testability of a combinational part of a Sequential Circuit. Algorithms of deriving test pairs for robust PDFs (Path Delay Faults) are suggested. The method is oriented to cut the path lengths of the obtained Circuits.
