The Experts below are selected from a list of 213 Experts worldwide ranked by ideXlab platform

Yukihiro Fujimoto - One of the best experts on this subject based on the ideXlab platform.

  • a current controlled latch sense amplifier and a static power saving Input Buffer for low power architecture
    IEEE Journal of Solid-state Circuits, 1993
    Co-Authors: T Kobayashi, Kazutaka Nogami, T Shirotori, Yukihiro Fujimoto
    Abstract:

    Two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described. One is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically. This sense amplifier reduces power without degrading access time compared with the conventional current-mirror sense amplifier. The other is a static power-saving Input Buffer (SPSIB) that reduces DC current in interface circuits receiving TTL high Input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM. >

  • a current mode latch sense amplifier and a static power saving Input Buffer for low power architecture
    Symposium on VLSI Circuits, 1992
    Co-Authors: T Kobayashi, Kazutaka Nogami, T Shirotori, Yukihiro Fujimoto, O Watanabe
    Abstract:

    Two circuit schemes for reducing power dissipation are proposed. The first is a current-mode latch sense amplifier that achieves power reduction without degradation of the access speed compared with conventional current-mirror sense amplifier operation. The other is a static power saving Input Buffer (SPSIB) for reducing static power. These circuits are applied to 512-kb high-speed SRAMs, and the efficiencies are simulated by SPICE simulations. The current-mode latch sense amplifier effectively reduces the power, and the SPSIB reduces current in the interface circuit. >

T Kobayashi - One of the best experts on this subject based on the ideXlab platform.

  • a current controlled latch sense amplifier and a static power saving Input Buffer for low power architecture
    IEEE Journal of Solid-state Circuits, 1993
    Co-Authors: T Kobayashi, Kazutaka Nogami, T Shirotori, Yukihiro Fujimoto
    Abstract:

    Two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described. One is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically. This sense amplifier reduces power without degrading access time compared with the conventional current-mirror sense amplifier. The other is a static power-saving Input Buffer (SPSIB) that reduces DC current in interface circuits receiving TTL high Input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM. >

  • a current mode latch sense amplifier and a static power saving Input Buffer for low power architecture
    Symposium on VLSI Circuits, 1992
    Co-Authors: T Kobayashi, Kazutaka Nogami, T Shirotori, Yukihiro Fujimoto, O Watanabe
    Abstract:

    Two circuit schemes for reducing power dissipation are proposed. The first is a current-mode latch sense amplifier that achieves power reduction without degradation of the access speed compared with conventional current-mirror sense amplifier operation. The other is a static power saving Input Buffer (SPSIB) for reducing static power. These circuits are applied to 512-kb high-speed SRAMs, and the efficiencies are simulated by SPICE simulations. The current-mode latch sense amplifier effectively reduces the power, and the SPSIB reduces current in the interface circuit. >

Kazutaka Nogami - One of the best experts on this subject based on the ideXlab platform.

  • a current controlled latch sense amplifier and a static power saving Input Buffer for low power architecture
    IEEE Journal of Solid-state Circuits, 1993
    Co-Authors: T Kobayashi, Kazutaka Nogami, T Shirotori, Yukihiro Fujimoto
    Abstract:

    Two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described. One is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically. This sense amplifier reduces power without degrading access time compared with the conventional current-mirror sense amplifier. The other is a static power-saving Input Buffer (SPSIB) that reduces DC current in interface circuits receiving TTL high Input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM. >

  • a current mode latch sense amplifier and a static power saving Input Buffer for low power architecture
    Symposium on VLSI Circuits, 1992
    Co-Authors: T Kobayashi, Kazutaka Nogami, T Shirotori, Yukihiro Fujimoto, O Watanabe
    Abstract:

    Two circuit schemes for reducing power dissipation are proposed. The first is a current-mode latch sense amplifier that achieves power reduction without degradation of the access speed compared with conventional current-mirror sense amplifier operation. The other is a static power saving Input Buffer (SPSIB) for reducing static power. These circuits are applied to 512-kb high-speed SRAMs, and the efficiencies are simulated by SPICE simulations. The current-mode latch sense amplifier effectively reduces the power, and the SPSIB reduces current in the interface circuit. >

T Shirotori - One of the best experts on this subject based on the ideXlab platform.

  • a current controlled latch sense amplifier and a static power saving Input Buffer for low power architecture
    IEEE Journal of Solid-state Circuits, 1993
    Co-Authors: T Kobayashi, Kazutaka Nogami, T Shirotori, Yukihiro Fujimoto
    Abstract:

    Two new power-saving schemes for high-performance VLSIs with a large-scale memory and many interface signals are described. One is a current-controlled latch sense amplifier that reduces the power dissipation by stopping sense current automatically. This sense amplifier reduces power without degrading access time compared with the conventional current-mirror sense amplifier. The other is a static power-saving Input Buffer (SPSIB) that reduces DC current in interface circuits receiving TTL high Input level. The effectiveness of these new circuits is demonstrated with a 512-kb high-speed SRAM. >

  • a current mode latch sense amplifier and a static power saving Input Buffer for low power architecture
    Symposium on VLSI Circuits, 1992
    Co-Authors: T Kobayashi, Kazutaka Nogami, T Shirotori, Yukihiro Fujimoto, O Watanabe
    Abstract:

    Two circuit schemes for reducing power dissipation are proposed. The first is a current-mode latch sense amplifier that achieves power reduction without degradation of the access speed compared with conventional current-mirror sense amplifier operation. The other is a static power saving Input Buffer (SPSIB) for reducing static power. These circuits are applied to 512-kb high-speed SRAMs, and the efficiencies are simulated by SPICE simulations. The current-mode latch sense amplifier effectively reduces the power, and the SPSIB reduces current in the interface circuit. >

O Watanabe - One of the best experts on this subject based on the ideXlab platform.

  • a current mode latch sense amplifier and a static power saving Input Buffer for low power architecture
    Symposium on VLSI Circuits, 1992
    Co-Authors: T Kobayashi, Kazutaka Nogami, T Shirotori, Yukihiro Fujimoto, O Watanabe
    Abstract:

    Two circuit schemes for reducing power dissipation are proposed. The first is a current-mode latch sense amplifier that achieves power reduction without degradation of the access speed compared with conventional current-mirror sense amplifier operation. The other is a static power saving Input Buffer (SPSIB) for reducing static power. These circuits are applied to 512-kb high-speed SRAMs, and the efficiencies are simulated by SPICE simulations. The current-mode latch sense amplifier effectively reduces the power, and the SPSIB reduces current in the interface circuit. >