The Experts below are selected from a list of 116169 Experts worldwide ranked by ideXlab platform
Harry I-an Chen - One of the best experts on this subject based on the ideXlab platform.
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Triple-threshold Static Power minimization technique in high-level synthesis using 90nm MTCMOS technology
2007Co-Authors: Harry I-an ChenAbstract:As CMOS System-on-Chips approach the limits of Power dissipation, Static Power has become dominant in a circuit's total Power dissipation. The Static Power is increasing exponentially as technology nodes shrink and is projected to exceed the dynamic Power within the near future. Techniques that use the multi-threshold CMOS (MTCMOS) technology have been developed to reduce Static Power effectively. In this thesis, a novel triple-threshold Static Power minimization technique in high-level synthesis has been developed using the 90nm MTCMOS technology. Using Static timing analysis, the optimal partitioning of gates with three different threshold voltages is determined via iterative analysis. The proposed triple-threshold technique has been applied to optimize several benchmark circuits, and the results show an average saving in Static Power close to 90% compared to un-optimized LVT designs. For all designs tested, the triple-threshold technique has produced designs with lower Static Power compared to a dual-threshold technique.
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PATMOS - Triple-threshold Static Power minimization in high-level synthesis of VLSI CMOS
Lecture Notes in Computer Science, 1Co-Authors: Harry I-an Chen, Edward K. W. Loo, James B. Kuo, Marek SyrzyckiAbstract:In this paper we present a new Static Power minimization technique exploiting the use of triple-threshold CMOS standard cell libraries in 90nm technology. Using Static timing analysis, we determine the timing requirements of cells and place cells with low and standard threshold voltages in the critical paths. Cells with a high threshold voltage are placed in non-critical paths to minimize the Static Power with no overall timing degradation. From the timing and Power analysis, we determine the optimal placement of high, standard and low threshold voltage cells. Using three different threshold voltages, an optimized triple-threshold 16-bit multiplier design featured 90% less Static Power compared to the pure low-threshold design and 54% less Static Power compared to the dual-threshold design.
Marek Syrzycki - One of the best experts on this subject based on the ideXlab platform.
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PATMOS - Triple-threshold Static Power minimization in high-level synthesis of VLSI CMOS
Lecture Notes in Computer Science, 1Co-Authors: Harry I-an Chen, Edward K. W. Loo, James B. Kuo, Marek SyrzyckiAbstract:In this paper we present a new Static Power minimization technique exploiting the use of triple-threshold CMOS standard cell libraries in 90nm technology. Using Static timing analysis, we determine the timing requirements of cells and place cells with low and standard threshold voltages in the critical paths. Cells with a high threshold voltage are placed in non-critical paths to minimize the Static Power with no overall timing degradation. From the timing and Power analysis, we determine the optimal placement of high, standard and low threshold voltage cells. Using three different threshold voltages, an optimized triple-threshold 16-bit multiplier design featured 90% less Static Power compared to the pure low-threshold design and 54% less Static Power compared to the dual-threshold design.
Amir Moradi - One of the best experts on this subject based on the ideXlab platform.
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Static Power Side-Channel Analysis—An Investigation of Measurement Factors
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2020Co-Authors: Thorben Moos, Amir Moradi, Bastian RichterAbstract:The Static Power consumption of modern CMOS devices has become a substantial concern in the context of the side-channel security of cryptographic hardware. Its continuous growth in nanometer-scaled technologies is not only inconvenient for effective low-Power designs but does also create a new target for Power analysis adversaries. Additionally, it has to be noted that several of the numerous sources of Static Power dissipation in CMOS circuits exhibit an exponential dependence on environmental factors which a classical Power analysis adversary is in control of. These factors include the operating conditions’ temperature and supply voltage. Furthermore, in the case of clock control, the measurement interval can be adjusted arbitrarily. Our experiments on a 150-nm CMOS ASIC reveal that with respect to the signal-to-noise ratio in Static Power side-channel analyses, stretching the measurement interval decreases the noise exponentially and even more importantly that raising the working temperature increases the signal exponentially. Control over the supply voltage has a far smaller, but still noticeable, positive impact as well. In summary, a Static Power analysis adversary can physically force a device to leak more information by controlling its operating environment and furthermore measure these leakages with arbitrary precision by modifying the interval length.
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Exploring the Effect of Device Aging on Static Power Analysis Attacks
2019Co-Authors: Naghmeh Karimi, Thorben Moos, Amir MoradiAbstract:Vulnerability of cryptographic devices to side-channel analysis attacks, and in particular Power analysis attacks has been extensively studied in the recent years. Among them, Static Power analysis attacks have become relevant with moving towards smaller technology nodes for which the Static Power is comparable to the dynamic Power of a chip, or even dominant in future technology generations. The magnitude of the Static Power of a chip depends on the physical characteristics of transistors (e.g., the dimensions) as well as operating conditions (e.g., the temperature) and the electrical specifications such as the threshold voltage. In fact, the electrical specifications of transistors deviate from their originally intended ones during device lifetime due to aging mechanisms. Although device aging has been extensively investigated from reliability point of view, the impact of aging on the security of devices, and in particular on the vulnerability of devices to Power analysis attacks are yet to be considered.This paper fills the gap and investigates how device aging can affect the susceptibility of a chip exposed to Static Power analysis attacks. To this end, we conduct both, simulation and practical experiments on real silicon. The experimental results are extracted from a realization of the PRESENT cipher fabricated using a 65nm commercial standard cell library. The results show that the amount of exploitable leakage through the Static Power consumption as a side channel is reduced when the device is aged. This can be considered as a positive development which can (even slightly) harden such Static Power analysis attacks. Additionally, this result is of great interest to Static Power side-channel adversaries since state-of-the-art leakage current measurements are conducted over long time periods under increased working temperatures and supply voltages to amplify the exploitable information, which certainly fuels aging-related device degradation.
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DATE - Static Power side-channel analysis of a threshold implementation prototype chip
Design Automation & Test in Europe Conference & Exhibition (DATE) 2017, 2017Co-Authors: Thorben Moos, Amir Moradi, Bastian RichterAbstract:The Static Power consumption of modern CMOS devices has become a substantial concern in the context of the side-channel security of cryptographic hardware. The continuous growth of the leakage Power dissipation in nanometer-scaled CMOS technologies is not only inconvenient for effective low Power designs, but does also create a new target for Power analysis adversaries. In this paper, we present the first experimental results of a Static Power side-channel analysis targeting an ASIC implementation of a provably first-order secure hardware masking scheme. The investigated 150 nm CMOS prototype chip realizes the PRESENT-80 lightweight block cipher as a threshold implementation and allows us to draw a comparison between the information leakage through its dynamic and Static Power consumption. By employing a sophisticated measurement setup dedicated to Static Power analysis, including a very low-noise DC amplifier as well as a climate chamber, we are able to recover the key of our target implementation with significantly less traces compared to the corresponding dynamic Power analysis attack. In particular, for a successful third-order attack exploiting the Static currents, less than 200 thousand traces are needed. Whereas for the same attack in the dynamic Power domain around 5 million measurements are required. Furthermore, we are able to show that only-first-order resistant approaches like the investigated threshold implementation do not significantly increase the complexity of a Static Power analysis. Therefore, we firmly believe that this side channel can actually become the target of choice for real-world adversaries against masking countermeasures implemented in advanced CMOS technologies.
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CHES - Side-Channel Leakage through Static Power
Advanced Information Systems Engineering, 2014Co-Authors: Amir MoradiAbstract:By shrinking the technology Static Power consumption of CMOS circuits is becoming a major concern. In this paper, we present the first practical results of exploiting Static Power consumption of FPGA-based cryptographic devices in order to mount a key-recovery side-channel attack. The experiments represented here are based on three Xilinx FPGAs built on 65 nm, 45 nm, and 28 nm process technologies. By means of a sophisticated measurement setup and methodology we demonstrate an exploitable information leakage through Static Power of the underlying FPGAs. The current work highlights the feasibility of side-channel analysis attacks by Static Power that have been known for years but have not been performed and investigated in practice yet. This is a starting point for further research investigations, and may have a significant impact on the efficiency of DPA countermeasures in the near future.
Gurindar S Sohi - One of the best experts on this subject based on the ideXlab platform.
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a Static Power model for architects
International Symposium on Microarchitecture, 2000Co-Authors: Adam J Butts, Gurindar S SohiAbstract:Static Power dissipation due to transistor leakage constitutes an increasing fraction of the total Power in modern semiconductor technologies. Current technology trends indicate that the contribution will increase rapidly, reaching one half of total Power dissipation within three process generations. Developing Power efficient products will require consideration of Static Power in the earliest phases of design, including architecture and microarchitecture definition. We propose a simple equation for estimating Static Power consumption at the architectural level: P/sub Static/=V/sub CC//spl middot/N/spl middot/k/sub design//spl middot/I/spl circ//sub leak/, where V/sub CC/ is the supply voltage, N is the number of transistors, k/sub design/ is a design dependent parameter, and I/spl circ//sub leak/ is a technology dependent parameter. This model enables high-level reasoning about the likely Static Power demands of alternative microarchitectures. Reasonably accurate values for the factors within the equation may be obtained directly from the high-level designs or by straightforward scaling arguments. The factors within the equation also suggest opportunities for Static Power optimization, including reducing the total number of devices, partitioning the design to allow for lower supply voltages or slower, less leaky transistors, turning off unused devices, favoring certain design styles, and favoring high bandwidth over low latency. Speculation is also examined as a means to employ slower transistors without a significant performance penalty.
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MICRO - A Static Power model for architects
Proceedings of the 33rd annual ACM IEEE international symposium on Microarchitecture - MICRO 33, 2000Co-Authors: J. Adam Butts, Gurindar S SohiAbstract:Static Power dissipation due to transistor leakage constitutes an increasing fraction of the total Power in modern semiconductor technologies. Current technology trends indicate that the contribution will increase rapidly, reaching one half of total Power dissipation within three process generations. Developing Power efficient products will require consideration of Static Power in the earliest phases of design, including architecture and microarchitecture definition. We propose a simple equation for estimating Static Power consumption at the architectural level: P/sub Static/=V/sub CC//spl middot/N/spl middot/k/sub design//spl middot/I/spl circ//sub leak/, where V/sub CC/ is the supply voltage, N is the number of transistors, k/sub design/ is a design dependent parameter, and I/spl circ//sub leak/ is a technology dependent parameter. This model enables high-level reasoning about the likely Static Power demands of alternative microarchitectures. Reasonably accurate values for the factors within the equation may be obtained directly from the high-level designs or by straightforward scaling arguments. The factors within the equation also suggest opportunities for Static Power optimization, including reducing the total number of devices, partitioning the design to allow for lower supply voltages or slower, less leaky transistors, turning off unused devices, favoring certain design styles, and favoring high bandwidth over low latency. Speculation is also examined as a means to employ slower transistors without a significant performance penalty.
Hiroki Iura - One of the best experts on this subject based on the ideXlab platform.
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VTC Spring - Static Power Allocation in Two-Hop MIMO Amplify-and-Forward Relay Systems
VTC Spring 2009 - IEEE 69th Vehicular Technology Conference, 2009Co-Authors: Philip Orlik, Jinyun Zhang, Toshiyuki Kuze, Hiroki IuraAbstract:In this paper, we propose a Static Power allocation algorithm for a two-hop multi-input-multi-output (MIMO) amplify-and-forward (AF) relay system in which the interim channel state information over the first and the second hops is unavailable. Based on the path losses over the first and the second hops, this algorithm performs Static Power allocation between the source and relay nodes to maximize the equivalent received SNR of the system. We further investigate the optimal location of the relay node when the conventional fixed and the proposed optimal Static Power allocation schemes are applied. Our comparison between direct transmission and relay-based two-hop transmission indicates that whether the latter outperforms the former depends on a tradeoff between the received SNR gain and the multiplexing loss in the relay-based two-hop transmission scheme.
