The Experts below are selected from a list of 2298 Experts worldwide ranked by ideXlab platform
Yao-wen Chang - One of the best experts on this subject based on the ideXlab platform.
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an optimal network flow based simultaneous diode and jumper Insertion Algorithm for antenna fixing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008Co-Authors: Zhewei Jiang, Yao-wen ChangAbstract:As technology enters the nanometer territory, the antenna effect plays an important role in determining the yield and reliability of a VLSI circuit. Diode and jumper Insertions are the most effective techniques to fix the antenna effect. However, due to the increasing design complexity and the limited routing resource, applying diode or jumper Insertion alone cannot achieve a high antenna fixing rate. In this paper, we give a polynomial-time antenna violation detection/fixing Algorithm by simultaneous diode and jumper Insertion with minimum cost, which is based on a minimum-cost network-flow formulation. Experimental results show that our Algorithm consistently achieves much higher antenna fixing rates than the state-of-the-art jumper and diode Insertion Algorithms alone.
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An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007Co-Authors: Bor-yiing Su, Yao-wen ChangAbstract:As the process technology enters the nanometer era, reliability has become a major concern in the design and manufacturing of very large-scale integration circuits. In this paper, we focus on one reliability issue-jumper Insertion in routing trees for avoiding/fixing antenna-effect violations at the routing/postlayout stages. We formulate the jumper Insertion for antenna avoidance/fixing as a tree-cutting problem and present the first optimal Algorithm for the tree-cutting problem. We show that the tree-cutting problem exhibits the properties of optimal substructures and greedy choices. With these properties, we present an O(V)-time optimal jumper-Insertion Algorithm that uses the minimum number of jumpers to avoid/fix the antenna violations in a routing tree with vertices. Experimental results show the superior effectiveness and efficiency of our Algorithm.
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an optimal jumper Insertion Algorithm for antenna avoidance fixing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007Co-Authors: Bor-yiing Su, Yao-wen ChangAbstract:As the process technology enters the nanometer era, reliability has become a major concern in the design and manufacturing of very large-scale integration circuits. In this paper, we focus on one reliability issue-jumper Insertion in routing trees for avoiding/fixing antenna-effect violations at the routing/postlayout stages. We formulate the jumper Insertion for antenna avoidance/fixing as a tree-cutting problem and present the first optimal Algorithm for the tree-cutting problem. We show that the tree-cutting problem exhibits the properties of optimal substructures and greedy choices. With these properties, we present an O(V)-time optimal jumper-Insertion Algorithm that uses the minimum number of jumpers to avoid/fix the antenna violations in a routing tree with vertices. Experimental results show the superior effectiveness and efficiency of our Algorithm.
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an exact jumper Insertion Algorithm for antenna violation avoidance fixing considering routing obstacles
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007Co-Authors: Bor-yiing Su, Yao-wen Chang, Jiang HuAbstract:We study in this paper the problem of jumper Insertion on general routing (Steiner/spanning) trees with obstacles for antenna avoidance/fixing at the routing and/or postlayout stages. We formulate the jumper Insertion for antenna avoidance/fixing as a tree-cutting problem and present the first optimal Algorithm for the general tree-cutting problem. We show that the tree-cutting problem exhibits the properties of optimal substructures and greedy choices. With these properties, we present an O((V+D)lgD)-time optimal jumper-Insertion Algorithm that uses the least number of jumpers to avoid/fix the antenna violations on a Steiner/spanning tree with V vertices and D obstacles. Experimental results show the superior effectiveness and efficiency of our Algorithm
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An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007Co-Authors: Bor-yiing Su, Yao-wen Chang, Jiang HuAbstract:We study in this paper the problem of jumper Insertion on general routing (Steiner/spanning) trees with obstacles for antenna avoidance/fixing at the routing and/or postlayout stages. We formulate the jumper Insertion for antenna avoidance/fixing as a tree-cutting problem and present the first optimal Algorithm for the general tree-cutting problem. We show that the tree-cutting problem exhibits the properties of optimal substructures and greedy choices. With these properties, we present an O((V+D)lgD)-time optimal jumper-Insertion Algorithm that uses the least number of jumpers to avoid/fix the antenna violations on a Steiner/spanning tree with V vertices and D obstacles. Experimental results show the superior effectiveness and efficiency of our Algorithm
Bor-yiing Su - One of the best experts on this subject based on the ideXlab platform.
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An Optimal Jumper-Insertion Algorithm for Antenna Avoidance/Fixing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007Co-Authors: Bor-yiing Su, Yao-wen ChangAbstract:As the process technology enters the nanometer era, reliability has become a major concern in the design and manufacturing of very large-scale integration circuits. In this paper, we focus on one reliability issue-jumper Insertion in routing trees for avoiding/fixing antenna-effect violations at the routing/postlayout stages. We formulate the jumper Insertion for antenna avoidance/fixing as a tree-cutting problem and present the first optimal Algorithm for the tree-cutting problem. We show that the tree-cutting problem exhibits the properties of optimal substructures and greedy choices. With these properties, we present an O(V)-time optimal jumper-Insertion Algorithm that uses the minimum number of jumpers to avoid/fix the antenna violations in a routing tree with vertices. Experimental results show the superior effectiveness and efficiency of our Algorithm.
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an optimal jumper Insertion Algorithm for antenna avoidance fixing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007Co-Authors: Bor-yiing Su, Yao-wen ChangAbstract:As the process technology enters the nanometer era, reliability has become a major concern in the design and manufacturing of very large-scale integration circuits. In this paper, we focus on one reliability issue-jumper Insertion in routing trees for avoiding/fixing antenna-effect violations at the routing/postlayout stages. We formulate the jumper Insertion for antenna avoidance/fixing as a tree-cutting problem and present the first optimal Algorithm for the tree-cutting problem. We show that the tree-cutting problem exhibits the properties of optimal substructures and greedy choices. With these properties, we present an O(V)-time optimal jumper-Insertion Algorithm that uses the minimum number of jumpers to avoid/fix the antenna violations in a routing tree with vertices. Experimental results show the superior effectiveness and efficiency of our Algorithm.
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an exact jumper Insertion Algorithm for antenna violation avoidance fixing considering routing obstacles
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007Co-Authors: Bor-yiing Su, Yao-wen Chang, Jiang HuAbstract:We study in this paper the problem of jumper Insertion on general routing (Steiner/spanning) trees with obstacles for antenna avoidance/fixing at the routing and/or postlayout stages. We formulate the jumper Insertion for antenna avoidance/fixing as a tree-cutting problem and present the first optimal Algorithm for the general tree-cutting problem. We show that the tree-cutting problem exhibits the properties of optimal substructures and greedy choices. With these properties, we present an O((V+D)lgD)-time optimal jumper-Insertion Algorithm that uses the least number of jumpers to avoid/fix the antenna violations on a Steiner/spanning tree with V vertices and D obstacles. Experimental results show the superior effectiveness and efficiency of our Algorithm
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An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007Co-Authors: Bor-yiing Su, Yao-wen Chang, Jiang HuAbstract:We study in this paper the problem of jumper Insertion on general routing (Steiner/spanning) trees with obstacles for antenna avoidance/fixing at the routing and/or postlayout stages. We formulate the jumper Insertion for antenna avoidance/fixing as a tree-cutting problem and present the first optimal Algorithm for the general tree-cutting problem. We show that the tree-cutting problem exhibits the properties of optimal substructures and greedy choices. With these properties, we present an O((V+D)lgD)-time optimal jumper-Insertion Algorithm that uses the least number of jumpers to avoid/fix the antenna violations on a Steiner/spanning tree with V vertices and D obstacles. Experimental results show the superior effectiveness and efficiency of our Algorithm
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an optimal jumper Insertion Algorithm for antenna avoidance fixing on general routing trees with obstacles
International Symposium on Physical Design, 2006Co-Authors: Bor-yiing Su, Yao-wen Chang, Jiang HuAbstract:We study in this paper the problem of jumper Insertion on general routing (Steiner/spanning) trees with obstacles for antenna avoidance/fixing at the routing and/or post-layout stages. We formulate the jumper Insertion for antenna avoidance/fixing as a tree-cutting problem and present the firstoptimal Algorithm for the general tree-cutting problem. We show that the tree-cutting problem exhibits the properties of optimal substructures and greedy choices. With these properties, we present an O((V+D) lg D)-time optimal jumper Insertion Algorithm that uses the least number of jumpers to avoid/fix the antenna violations on a Steiner/spanning tree with V vertices and D obstacles. Experimental results show the superior effectiveness and efficiency of our Algorithm.
Jiang Hu - One of the best experts on this subject based on the ideXlab platform.
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an exact jumper Insertion Algorithm for antenna violation avoidance fixing considering routing obstacles
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007Co-Authors: Bor-yiing Su, Yao-wen Chang, Jiang HuAbstract:We study in this paper the problem of jumper Insertion on general routing (Steiner/spanning) trees with obstacles for antenna avoidance/fixing at the routing and/or postlayout stages. We formulate the jumper Insertion for antenna avoidance/fixing as a tree-cutting problem and present the first optimal Algorithm for the general tree-cutting problem. We show that the tree-cutting problem exhibits the properties of optimal substructures and greedy choices. With these properties, we present an O((V+D)lgD)-time optimal jumper-Insertion Algorithm that uses the least number of jumpers to avoid/fix the antenna violations on a Steiner/spanning tree with V vertices and D obstacles. Experimental results show the superior effectiveness and efficiency of our Algorithm
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An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007Co-Authors: Bor-yiing Su, Yao-wen Chang, Jiang HuAbstract:We study in this paper the problem of jumper Insertion on general routing (Steiner/spanning) trees with obstacles for antenna avoidance/fixing at the routing and/or postlayout stages. We formulate the jumper Insertion for antenna avoidance/fixing as a tree-cutting problem and present the first optimal Algorithm for the general tree-cutting problem. We show that the tree-cutting problem exhibits the properties of optimal substructures and greedy choices. With these properties, we present an O((V+D)lgD)-time optimal jumper-Insertion Algorithm that uses the least number of jumpers to avoid/fix the antenna violations on a Steiner/spanning tree with V vertices and D obstacles. Experimental results show the superior effectiveness and efficiency of our Algorithm
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a new rlc buffer Insertion Algorithm
International Conference on Computer Aided Design, 2006Co-Authors: Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo LiAbstract:Most existing buffering Algorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. Even for the approaches considering inductance effects, their delay models are too simplistic to catch the actual performance. As delay-length dependence is approaching linear with inductance effect (Ismail and Friedman, 1999), fewer buffers are needed to reduce RLC delay. This motivates this work to propose a new Algorithm for RLC buffer Insertion. In this paper, a new buffer Insertion Algorithm considering inductance for intermediate and global interconnect is proposed, based on downstream impedance instead of traditional downstream capacitance. A new pruning technique that provides tremendous speedup and a new frequency estimation method that is very accurate in delay computation are also proposed. Experiments on industrial netlists demonstrate that our new Algorithm reduces the number of buffers up to 34.4% over the traditional van Ginneken's Algorithm that ignores inductance. Our impedance delay estimation is very accurate compared to SPICE simulations, with only 10% error while the delay model used in the previous RLC Algorithm has 20% error (Ismael et al., 2001). The accurate delay model not only reduces the number of buffers, but also brings high fidelity to the buffer solutions. Incorporating slew constraints, the Algorithm is accelerated by about 4times with only slight degradation in solution quality
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ICCAD - A new RLC buffer Insertion Algorithm
Proceedings of the 2006 IEEE ACM international conference on Computer-aided design - ICCAD '06, 2006Co-Authors: Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo LiAbstract:Most existing buffering Algorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. Even for the approaches considering inductance effects, their delay models are too simplistic to catch the actual performance. As delay-length dependence is approaching linear with inductance effect (Ismail and Friedman, 1999), fewer buffers are needed to reduce RLC delay. This motivates this work to propose a new Algorithm for RLC buffer Insertion. In this paper, a new buffer Insertion Algorithm considering inductance for intermediate and global interconnect is proposed, based on downstream impedance instead of traditional downstream capacitance. A new pruning technique that provides tremendous speedup and a new frequency estimation method that is very accurate in delay computation are also proposed. Experiments on industrial netlists demonstrate that our new Algorithm reduces the number of buffers up to 34.4% over the traditional van Ginneken's Algorithm that ignores inductance. Our impedance delay estimation is very accurate compared to SPICE simulations, with only 10% error while the delay model used in the previous RLC Algorithm has 20% error (Ismael et al., 2001). The accurate delay model not only reduces the number of buffers, but also brings high fidelity to the buffer solutions. Incorporating slew constraints, the Algorithm is accelerated by about 4times with only slight degradation in solution quality
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an optimal jumper Insertion Algorithm for antenna avoidance fixing on general routing trees with obstacles
International Symposium on Physical Design, 2006Co-Authors: Bor-yiing Su, Yao-wen Chang, Jiang HuAbstract:We study in this paper the problem of jumper Insertion on general routing (Steiner/spanning) trees with obstacles for antenna avoidance/fixing at the routing and/or post-layout stages. We formulate the jumper Insertion for antenna avoidance/fixing as a tree-cutting problem and present the firstoptimal Algorithm for the general tree-cutting problem. We show that the tree-cutting problem exhibits the properties of optimal substructures and greedy choices. With these properties, we present an O((V+D) lg D)-time optimal jumper Insertion Algorithm that uses the least number of jumpers to avoid/fix the antenna violations on a Steiner/spanning tree with V vertices and D obstacles. Experimental results show the superior effectiveness and efficiency of our Algorithm.
Zhuo Li - One of the best experts on this subject based on the ideXlab platform.
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an o bn 2 time Algorithm for optimal buffer Insertion with b buffer types
arXiv: Hardware Architecture, 2007Co-Authors: Zhuo LiAbstract:Buffer Insertion is a popular technique to reduce the interconnect delay. The classic buffer Insertion Algorithm of van Ginneken has time complexity O(n^2), where n is the number of buffer positions. Lillis, Cheng and Lin extended van Ginneken's Algorithm to allow b buffer types in time O (b^2 n^2). For modern design libraries that contain hundreds of buffers, it is a serious challenge to balance the speed and performance of the buffer Insertion Algorithm. In this paper, we present a new Algorithm that computes the optimal buffer Insertion in O (bn^2) time. The reduction is achieved by the observation that the (Q, C) pairs of the candidates that generate the new candidates must form a convex hull. On industrial test cases, the new Algorithm is faster than the previous best buffer Insertion Algorithms by orders of magnitude.
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a new rlc buffer Insertion Algorithm
International Conference on Computer Aided Design, 2006Co-Authors: Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo LiAbstract:Most existing buffering Algorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. Even for the approaches considering inductance effects, their delay models are too simplistic to catch the actual performance. As delay-length dependence is approaching linear with inductance effect (Ismail and Friedman, 1999), fewer buffers are needed to reduce RLC delay. This motivates this work to propose a new Algorithm for RLC buffer Insertion. In this paper, a new buffer Insertion Algorithm considering inductance for intermediate and global interconnect is proposed, based on downstream impedance instead of traditional downstream capacitance. A new pruning technique that provides tremendous speedup and a new frequency estimation method that is very accurate in delay computation are also proposed. Experiments on industrial netlists demonstrate that our new Algorithm reduces the number of buffers up to 34.4% over the traditional van Ginneken's Algorithm that ignores inductance. Our impedance delay estimation is very accurate compared to SPICE simulations, with only 10% error while the delay model used in the previous RLC Algorithm has 20% error (Ismael et al., 2001). The accurate delay model not only reduces the number of buffers, but also brings high fidelity to the buffer solutions. Incorporating slew constraints, the Algorithm is accelerated by about 4times with only slight degradation in solution quality
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ICCAD - A new RLC buffer Insertion Algorithm
Proceedings of the 2006 IEEE ACM international conference on Computer-aided design - ICCAD '06, 2006Co-Authors: Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo LiAbstract:Most existing buffering Algorithms neglect the impact of inductance on circuit performance, which causes large error in circuit analysis and optimization. Even for the approaches considering inductance effects, their delay models are too simplistic to catch the actual performance. As delay-length dependence is approaching linear with inductance effect (Ismail and Friedman, 1999), fewer buffers are needed to reduce RLC delay. This motivates this work to propose a new Algorithm for RLC buffer Insertion. In this paper, a new buffer Insertion Algorithm considering inductance for intermediate and global interconnect is proposed, based on downstream impedance instead of traditional downstream capacitance. A new pruning technique that provides tremendous speedup and a new frequency estimation method that is very accurate in delay computation are also proposed. Experiments on industrial netlists demonstrate that our new Algorithm reduces the number of buffers up to 34.4% over the traditional van Ginneken's Algorithm that ignores inductance. Our impedance delay estimation is very accurate compared to SPICE simulations, with only 10% error while the delay model used in the previous RLC Algorithm has 20% error (Ismael et al., 2001). The accurate delay model not only reduces the number of buffers, but also brings high fidelity to the buffer solutions. Incorporating slew constraints, the Algorithm is accelerated by about 4times with only slight degradation in solution quality
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an o bn sup 2 time Algorithm for optimal buffer Insertion with b buffer types
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2006Co-Authors: Zhuo LiAbstract:Buffer Insertion is a popular technique to reduce the interconnect delay. The classic buffer Insertion Algorithm of van Ginneken has a time complexity of O(n/sup 2/), where n is the number of buffer positions. Lillis, Cheng, and Lin extended van Ginneken's Algorithm to allow b buffer types in O(b/sup 2/n/sup 2/) time. For modern design libraries that contain hundreds of buffers, it is a serious challenge to balance the speed and performance of the buffer Insertion Algorithm. In this paper, we present a new Algorithm that computes the optimal buffer Insertion in O(bn/sup 2/) time. The reduction is achieved by the observation that the (Q,C) pairs of the candidates that generate the new candidates must form a convex hull. On industrial test cases, the new Algorithm is faster than the previous best buffer Insertion Algorithms by orders of magnitude. Since van Ginneken's Algorithm with multiple buffer types are used by most existing Algorithms on buffer Insertion and buffer sizing, our new Algorithm improves the performance of all these Algorithms.
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an o bn sup 2 time Algorithm for optimal buffer Insertion with b buffer types
Design Automation and Test in Europe, 2005Co-Authors: Zhuo LiAbstract:Buffer Insertion is a popular technique to reduce interconnect delay. The classic buffer Insertion Algorithm of L.P.P.P. van Ginneken (see ISCAS, p.865-8, 1990) has time complexity O(n/sup 2/), where n is the number of buffer positions. J. Lillis et al. (see IEEE Trans. Solid-Slate Circuits, vol.31, no.3, p.437-47, 1996) extended van Ginneken's Algorithm to allow b buffer types in time O(b/sup 2/n/sup 2/). For modern design libraries that contain hundreds of buffers, it is a serious challenge to balance the speed and performance of the buffer Insertion Algorithm. We present a new Algorithm that computes the optimal buffer Insertion in O(bn/sup 2/) time. The reduction is achieved by the observation that the (Q, C) pairs of the candidates that generate the new candidates must form a convex hull. On industrial test cases, the new Algorithm is faster than the previous best buffer Insertion Algorithms by orders of magnitude.
Minyou Wu - One of the best experts on this subject based on the ideXlab platform.
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a combinatorial Insertion Algorithm for the public vehicle system
Vehicular Technology Conference, 2016Co-Authors: Ning Li, Linghe Kong, Jialiang Lu, Minyou WuAbstract:In Intelligent Transport field, the Public Vehicle System is proposed to introduce a concept of a specialized vehicle for public transportation, which can integrate and substitute for vehicles such as taxis, buses and railways. Public Vehicle model has several advantages over earlier models, but the Algorithm proposed in the model can't consider all potential solutions when building new paths, resulting in a decrease in performance. We expand the searching method to cover all cases of Insertion and achieve a lower cost. Our simulations show that the Combinatorial Insertion Algorithm can have a 5%-11% promotion in total traveling distance.
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VTC Spring - A Combinatorial Insertion Algorithm for the Public Vehicle System
2016 IEEE 83rd Vehicular Technology Conference (VTC Spring), 2016Co-Authors: Ning Li, Linghe Kong, Jialiang Lu, Minyou WuAbstract:In Intelligent Transport field, the Public Vehicle System is proposed to introduce a concept of a specialized vehicle for public transportation, which can integrate and substitute for vehicles such as taxis, buses and railways. Public Vehicle model has several advantages over earlier models, but the Algorithm proposed in the model can't consider all potential solutions when building new paths, resulting in a decrease in performance. We expand the searching method to cover all cases of Insertion and achieve a lower cost. Our simulations show that the Combinatorial Insertion Algorithm can have a 5%-11% promotion in total traveling distance.
