The Experts below are selected from a list of 3273 Experts worldwide ranked by ideXlab platform
S. Vrudhula - One of the best experts on this subject based on the ideXlab platform.
-
Variational Interconnect Delay metrics for statistical timing analysis
7th International Symposium on Quality Electronic Design (ISQED'06), 2006Co-Authors: P. Ghanta, S. VrudhulaAbstract:For statistical timing analysis and physical design optimization, Interconnect Delay metrics that model the Delay as a function of the metal process variations are very important. Accurate linear or at most second order Delay models in terms of the process variables are necessary to efficiently propagate uncertainty in the state-of-the-art VLSI designs with millions of transistors and on chip Interconnects. In this paper, we develop a method to extend the traditional moment based Delay analysis of Interconnects to consider the impact of Gaussian metal process variations and obtain mean-square optimal linear Delay models for Interconnects. We consider linear models for the variations in the conductance and capacitance of Interconnects and represent the moments (m0, m1, m2) of the Interconnect impulse response as a first order orthogonal polynomial series expansion in the process variables. We obtain the coefficients of the expansion by using the Galerkin residual error minimization method on the recursive equations that relate the Interconnect moments (m0, m1 , m2). We compare the accuracy of our approach against SPICE based Monte Carlo simulations and demonstrate a good match
-
ISQED - Variational Interconnect Delay Metrics for Statistical Timing Analysis
7th International Symposium on Quality Electronic Design (ISQED'06), 2006Co-Authors: P. Ghanta, S. VrudhulaAbstract:For statistical timing analysis and physical design optimization, Interconnect Delay metrics that model the Delay as a function of the metal process variations are very important. Accurate linear or at most second order Delay models in terms of the process variables are necessary to efficiently propagate uncertainty in the state-of-the-art VLSI designs with millions of transistors and on chip Interconnects. In this paper, we develop a method to extend the traditional moment based Delay analysis of Interconnects to consider the impact of Gaussian metal process variations and obtain mean-square optimal linear Delay models for Interconnects. We consider linear models for the variations in the conductance and capacitance of Interconnects and represent the moments (m/sub 0/, m/sub 1/, m/sub 2/) of the Interconnect impulse response as a first order orthogonal polynomial series expansion in the process variables. We obtain the coefficients of the expansion by using the Galerkin residual error minimization method on the recursive equations that relate the Interconnect moments (m/sub 0/, m/sub 1/, m/sub 2/). We compare the accuracy of our approach against SPICE based Monte Carlo simulations and demonstrate a good match.
-
variational Delay metrics for Interconnect timing analysis
Design Automation Conference, 2004Co-Authors: Kanak B Agarwal, Dennis Sylvester, David Blaauw, Sani R Nassif, S. VrudhulaAbstract:In this paper we develop an approach to model Interconnect Delay under process variability for timing analysis and physical design optimization. The technique allows for closed-form computation of Interconnect Delay probability density functions (PDFs) given variations in relevant process parameters such as linewidth, metal thickness, and dielectric thickness. We express the resistance and capacitance of a line as a linear function of random variables and then use these to compute circuit moments. Finally, these variability-aware moments are used in known closed-form Delay metrics to compute Interconnect Delay PDFs. We compare the approach to SPICE based Monte Carlo simulations and report an error in mean and standard deviation of Delay of 1% and 4% on average, respectively.
-
DAC - Variational Delay metrics for Interconnect timing analysis
Proceedings of the 41st annual conference on Design automation - DAC '04, 2004Co-Authors: Kanak B Agarwal, Dennis Sylvester, David Blaauw, Sani R Nassif, S. VrudhulaAbstract:In this paper we develop an approach to model Interconnect Delay under process variability for timing analysis and physical design optimization. The technique allows for closed-form computation of Interconnect Delay probability density functions (PDFs) given variations in relevant process parameters such as linewidth, metal thickness, and dielectric thickness. We express the resistance and capacitance of a line as a linear function of random variables and then use these to compute circuit moments. Finally, these variability-aware moments are used in known closed-form Delay metrics to compute Interconnect Delay PDFs. We compare the approach to SPICE based Monte Carlo simulations and report an error in mean and standard deviation of Delay of 1% and 4% on average, respectively.
Peng Li - One of the best experts on this subject based on the ideXlab platform.
-
Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007Co-Authors: Xiaoji Ye, Peng LiAbstract:Interconnects constitute a dominant source of circuit Delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in Interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical Interconnect Delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process variations are directly mapped into the variability of the output Delay and slew. An efficient method based on sensitivity analysis is implemented to calculate driving point models under variations for gate-level timing analysis. The proposed adjoint technique not only provides statistical performance variations of the Interconnect network under analysis, but also produces Delay and slew expressions parameterized in the underlying process variations in a quadratic parametric form. As such, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations.
-
ICCAD - Practical variation-aware Interconnect Delay and slew analysis for statistical timing verification
Proceedings of the 2006 IEEE ACM international conference on Computer-aided design - ICCAD '06, 2006Co-Authors: Xiaoji Ye, Peng LiAbstract:Interconnects constitute a dominant source of circuit Delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in Interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical Interconnect Delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process and input signal variations are directly mapped into the variability of the output Delay and slew. Since our approach produces Delay and slew expressions parameterized in the underlying process variations, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations.
-
Practical Variation-Aware Interconnect Delay and Slew Analysis for Statistical Timing Verification
2006 IEEE ACM International Conference on Computer Aided Design, 2006Co-Authors: Xiaoji Ye, Peng LiAbstract:Interconnects constitute a dominant source of circuit Delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in Interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical Interconnect Delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process and input signal variations are directly mapped into the variability of the output Delay and slew. Since our approach produces Delay and slew expressions parameterized in the underlying process variations, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations
Xiaoji Ye - One of the best experts on this subject based on the ideXlab platform.
-
Fast Variational Interconnect Delay and Slew Computation Using Quadratic Models
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2007Co-Authors: Xiaoji Ye, Peng LiAbstract:Interconnects constitute a dominant source of circuit Delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in Interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical Interconnect Delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process variations are directly mapped into the variability of the output Delay and slew. An efficient method based on sensitivity analysis is implemented to calculate driving point models under variations for gate-level timing analysis. The proposed adjoint technique not only provides statistical performance variations of the Interconnect network under analysis, but also produces Delay and slew expressions parameterized in the underlying process variations in a quadratic parametric form. As such, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations.
-
ICCAD - Practical variation-aware Interconnect Delay and slew analysis for statistical timing verification
Proceedings of the 2006 IEEE ACM international conference on Computer-aided design - ICCAD '06, 2006Co-Authors: Xiaoji Ye, Peng LiAbstract:Interconnects constitute a dominant source of circuit Delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in Interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical Interconnect Delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process and input signal variations are directly mapped into the variability of the output Delay and slew. Since our approach produces Delay and slew expressions parameterized in the underlying process variations, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations.
-
Practical Variation-Aware Interconnect Delay and Slew Analysis for Statistical Timing Verification
2006 IEEE ACM International Conference on Computer Aided Design, 2006Co-Authors: Xiaoji Ye, Peng LiAbstract:Interconnects constitute a dominant source of circuit Delay for modern chip designs. The variations of critical dimensions in modern VLSI technologies lead to variability in Interconnect performance that must be fully accounted for in timing verification. However, handling a multitude of inter-die/intra-die variations and assessing their impacts on circuit performance can dramatically complicate the timing analysis. In this paper, a practical Interconnect Delay and slew analysis technique is presented to facilitate efficient evaluation of wire performance variability. By harnessing a collection of computationally efficient procedures and closed-form formulas, process and input signal variations are directly mapped into the variability of the output Delay and slew. Since our approach produces Delay and slew expressions parameterized in the underlying process variations, it can be harnessed to enable statistical timing analysis while considering important statistical correlations. Our experimental results have indicated that the presented analysis is accurate regardless of location of sink nodes and it is also robust over a wide range of process variations
E.g. Friedman - One of the best experts on this subject based on the ideXlab platform.
-
Via placement for minimum Interconnect Delay in three-dimensional (3D) circuits
2006 IEEE International Symposium on Circuits and Systems, 2006Co-Authors: V.f. Pavlidis, E.g. FriedmanAbstract:The propagation Delay of interlayer 3D Interconnects is investigated in this paper. For RC Interconnects connecting two circuits located on different physical planes, the Interconnect Delay is minimized by optimally placing the non-stacked interlayer vias. The problem of determining this optimum via locations under the Elmore Delay model is described as a geometric program. Simulations indicate Delay improvements of up to 26% for relatively short Interconnect. The proposed approach is also compared with a wire sizing algorithm. Timing-driven via placement exhibits better results both in terms of Delay and power consumption
-
ISCAS - Via placement for minimum Interconnect Delay in three-dimensional (3D) circuits
2006 IEEE International Symposium on Circuits and Systems, 2006Co-Authors: V.f. Pavlidis, E.g. FriedmanAbstract:The propagation Delay of interlayer 3D Interconnects is investigated in this paper. For RC Interconnects connecting two circuits located on different physical planes, the Interconnect Delay is minimized by optimally placing the non-stacked interlayer vias. The problem of determining this optimum via locations under the Elmore Delay model is described as a geometric program. Simulations indicate Delay improvements of up to 26% for relatively short Interconnect. The proposed approach is also compared with a wire sizing algorithm. Timing-driven via placement exhibits better results both in terms of Delay and power consumption.
-
retiming with non zero clock skew variable register and Interconnect Delay
International Conference on Computer Aided Design, 1994Co-Authors: Tolga Soyata, E.g. FriedmanAbstract:A retiming algorithm is presented which includes the effects of variable register, clock distribution, and Interconnect Delay. These Delay components are incorporated into retiming by assigning Register Electrical Characteristics (RECs) to each edge in the graph representation of the synchronous circuit. A matrix (called the Sequential Adjacency Matrix or SAM) is presented that contains all path Delays. Timing constraints for each data path are derived from this matrix. Vertex lags are assigned ranges rather than single values as in standard retiming algorithms. The approach used in the proposed algorithm is to initialize these ranges with unbounded values and continuously tighten these ranges using localized timing constraints until an optimal solution is obtained. The algorithm is demonstrated on modified MCNC benchmark circuits and both increased clock frequencies and elimination of all race conditions are observed.
-
ICCAD - Retiming with non-zero clock skew, variable register, and Interconnect Delay
IEEE ACM International Conference on Computer-Aided Design, 1994Co-Authors: Tolga Soyata, E.g. FriedmanAbstract:A retiming algorithm is presented which includes the effects of variable register, clock distribution, and Interconnect Delay. These Delay components are incorporated into retiming by assigning Register Electrical Characteristics (RECs) to each edge in the graph representation of the synchronous circuit. A matrix (called the Sequential Adjacency Matrix or SAM) is presented that contains all path Delays. Timing constraints for each data path are derived from this matrix. Vertex lags are assigned ranges rather than single values as in standard retiming algorithms. The approach used in the proposed algorithm is to initialize these ranges with unbounded values and continuously tighten these ranges using localized timing constraints until an optimal solution is obtained. The algorithm is demonstrated on modified MCNC benchmark circuits and both increased clock frequencies and elimination of all race conditions are observed.
Nick Van Der Meijs - One of the best experts on this subject based on the ideXlab platform.
-
ASP-DAC - Crosstalk-aware statistical Interconnect Delay calculation
17th Asia and South Pacific Design Automation Conference, 2012Co-Authors: Qin Tang, Amir Zjajo, Michel Berkelaar, Nick Van Der MeijsAbstract:As the device geometries are shrinking, the impact of crosstalk effects increases, which results in a stronger dependence of Interconnect Delay on the input arrival time difference between victim and aggressor inputs (input skew). The increasing process variations lead to statistical input skew which induces significant Interconnect Delay variations. Therefore, it is necessary to take input skew variation into account for Interconnect Delay calculation in the presence of process variations. Existing timing analysis tools evaluate gate and Interconnect Delays separately. In this paper, we focus on statistical Interconnect Delay calculation considering crosstalk effects. A piecewise linear Delay-change-curve model enables closed-form analytical evaluation of the statistical Interconnect Delay caused by input skew (SK) variations. This method can handle arbitrarily distributed SK variations. The process-variation (PV)-induced Interconnect Delay variation is handled in a quadratic Delay model which considers coupling effects. The SK- and PV-induced Interconnect Delay variations are combined together for crosstalk-aware statistical Interconnect Delay calculation. The experimental results indicate that the proposed method can predict the Interconnect Delay impacted by both input skew variation and process variations with average (maximum) absolute mean error 0.25% (0.75%) and standard deviation error 1.31% (3.53%) for different types of coupled wires in a 65nm technology.
-
Crosstalk-aware statistical Interconnect Delay calculation
17th Asia and South Pacific Design Automation Conference, 2012Co-Authors: Qin Tang, Amir Zjajo, Michel Berkelaar, Nick Van Der MeijsAbstract:As the device geometries are shrinking, the impact of crosstalk effects increases, which results in a stronger dependence of Interconnect Delay on the input arrival time difference between victim and aggressor inputs (input skew). The increasing process variations lead to statistical input skew which induces significant Interconnect Delay variations. Therefore, it is necessary to take input skew variation into account for Interconnect Delay calculation in the presence of process variations. Existing timing analysis tools evaluate gate and Interconnect Delays separately. In this paper, we focus on statistical Interconnect Delay calculation considering crosstalk effects. A piecewise linear Delay-change-curve model enables closed-form analytical evaluation of the statistical Interconnect Delay caused by input skew (SK) variations. This method can handle arbitrarily distributed SK variations. The process-variation (PV)-induced Interconnect Delay variation is handled in a quadratic Delay model which considers coupling effects. The SK- and PV-induced Interconnect Delay variations are combined together for crosstalk-aware statistical Interconnect Delay calculation. The experimental results indicate that the proposed method can predict the Interconnect Delay impacted by both input skew variation and process variations with average (maximum) absolute mean error 0.25% (0.75%) and standard deviation error 1.31% (3.53%) for different types of coupled wires in a 65nm technology.
