The Experts below are selected from a list of 189 Experts worldwide ranked by ideXlab platform
Yongkyu Jung - One of the best experts on this subject based on the ideXlab platform.
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Hardware/Software Co-reconfigurable Instruction Decoder for Adaptive Multi-core DSP Architectures
Journal of Signal Processing Systems, 2011Co-Authors: Yongkyu JungAbstract:A programmable Instruction Decoder (PID) is introduced for designing adaptive multi-core DSP architectures by using a hardware/software co-reconfigurable approach without employing programmable devices. This PID permits DSP software developers for post-manufacturing modification of their DSP Instruction sets to add their application-specific Instructions whenever necessary. In addition, PID offers software developers an enhanced means to utilize the underlying DSP architectures by rescheduling implemented micro-operations for their tailored Instructions in the DSP processors. Thus, emerging DSP applications can be swiftly and efficiently re-imported to PID-based DSP processors without re-fabrication of new DSP chips. In addition to Instruction-level modification, an innovative Instruction-packing procedure for PID is presented for further enhancement of the PID-based DSP systems. PID architecture was developed and implemented in VHDL. The PID-based DSP systems were also developed and evaluated to demonstrate various post-manufacturing adaptabilities in DSP processor systems. Various multi-core DSP architectures based on Texas Instruments’ TMS320C55 DSP processor were used for evaluating performance and adaptability of this new programmable Instruction Decoder.
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hardware software co reconfigurable Instruction Decoder for adaptive multi core dsp architectures
Signal Processing Systems, 2011Co-Authors: Yongkyu JungAbstract:A programmable Instruction Decoder (PID) is introduced for designing adaptive multi-core DSP architectures by using a hardware/software co-reconfigurable approach without employing programmable devices. This PID permits DSP software developers for post-manufacturing modification of their DSP Instruction sets to add their application-specific Instructions whenever necessary. In addition, PID offers software developers an enhanced means to utilize the underlying DSP architectures by rescheduling implemented micro-operations for their tailored Instructions in the DSP processors. Thus, emerging DSP applications can be swiftly and efficiently re-imported to PID-based DSP processors without re-fabrication of new DSP chips. In addition to Instruction-level modification, an innovative Instruction-packing procedure for PID is presented for further enhancement of the PID-based DSP systems. PID architecture was developed and implemented in VHDL. The PID-based DSP systems were also developed and evaluated to demonstrate various post-manufacturing adaptabilities in DSP processor systems. Various multi-core DSP architectures based on Texas Instruments' TMS320C55 DSP processor were used for evaluating performance and adaptability of this new programmable Instruction Decoder.
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ESTImedia - A Hardware/Software Co-reconfigurable Multimedia Architecture
2006 IEEE ACM IFIP Workshop on Embedded Systems for Real Time Multimedia, 2006Co-Authors: Yongkyu JungAbstract:The hardware/software co-reconfiguration technique is introduced to design a reconfigurable multimedia architecture that does not employ field-programmable devices. This co-reconfiguration technique does not require modifying existing compilers to retarget their new multimedia processors. This technique allows software developers to rapidly retarget their multimedia processors. In order to present the reconfiguration procedures and performance evaluations of the technique, a smart Instruction Decoder for Texas Instruments' OMAP2420 was implemented and optimized.
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desing and optimization of a programmable Instruction Decoder for dsp architecture
Signal Processing Systems, 2006Co-Authors: Yongkyu JungAbstract:A hardware/software co-reconfiguration technique is introduced to design a programmable Instruction Decoder for DSP systems that do not employ field-programmable gate-array. This technique allows software developers to swiftly and accurately retarget their DSP systems. In order to present the reconfiguration procedures and performance evaluations of the technique, a reconfigurable Instruction Decoder (RID) for Texas Instruments' TMS320C55 DSPs was implemented and optimized.
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SiPS - Desing and Optimization of a Programmable Instruction Decoder for DSP Architecture
2006 IEEE Workshop on Signal Processing Systems Design and Implementation, 2006Co-Authors: Yongkyu JungAbstract:A hardware/software co-reconfiguration technique is introduced to design a programmable Instruction Decoder for DSP systems that do not employ field-programmable gate-array. This technique allows software developers to swiftly and accurately retarget their DSP systems. In order to present the reconfiguration procedures and performance evaluations of the technique, a reconfigurable Instruction Decoder (RID) for Texas Instruments' TMS320C55 DSPs was implemented and optimized.
Ricardo Santos - One of the best experts on this subject based on the ideXlab platform.
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SoCC - Instruction Decoders based on pattern factorization
2015 28th IEEE International System-on-Chip Conference (SOCC), 2015Co-Authors: Ricardo Santos, Renan Marks, Felipe Araújo, Rafael Alves, Renato SantosAbstract:This work presents the design of hardware Instruction Decoders based on the Pattern Based Instruction Word (PBIW) encoding technique. Instruction Decoder circuits have been designed in the datapath of ρ-VEX and the Leon3 soft-core embedded processors. The PBIW encoding scheme focuses on extracting out patterns from original Instructions at compiler time. The PBIW hardware Decoder works on the processor datapath simplifying the decoding Instruction logic by exploring the hardware parallelism between Instruction decoding and register read. The experiments show that the Instruction Decoders based on the PBIW technique present small impacts on area, dynamic power, and timing (3%–10% decrease on clock frequency) on the processor design.
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WSCAD-SSC - Design and Implementation of the PBIW Instruction Decoder in a Softcore Embedded Processor
2012 13th Symposium on Computer Systems, 2012Co-Authors: Renan Marks, Felipe Araújo, Renato Santos, Felipe Yonehara, Ricardo SantosAbstract:This paper presents the PBIW (Pattern Based Instruction Word) Instruction encoding technique on the \RVEX embedded soft core processor. The PBIW encoding technique maps the assembly generated by a compiler into an encoding scheme of a target processor. The results obtained shows that the PBIW encoding has a compression ratio ranging from 60.97% to 115.91% among the evaluated programs. The impact of PBIW encoding in the memory access shows significant performance gains since there are improvements in hit ratio up to 58.93%. The PBIW Decoder experiments show that the adoption of PBIW Decoder circuit shrinks the processor total area in 15% (on average) and dynamic power reduction in 40%. In addition, the PBIW Decoder reduces 56% and 52% the dynamic power consumption and the amount of data stored (memory bits of M4K memory blocks) in the Instruction memory.
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Design and Implementation of the PBIW Instruction Decoder in a Softcore Embedded Processor
2012 13th Symposium on Computer Systems, 2012Co-Authors: Renan Marks, Felipe Araújo, Renato Santos, Felipe Yonehara, Ricardo SantosAbstract:This paper presents the PBIW (Pattern Based Instruction Word) Instruction encoding technique on the \RVEX embedded soft core processor. The PBIW encoding technique maps the assembly generated by a compiler into an encoding scheme of a target processor. The results obtained shows that the PBIW encoding has a compression ratio ranging from 60.97% to 115.91% among the evaluated programs. The impact of PBIW encoding in the memory access shows significant performance gains since there are improvements in hit ratio up to 58.93%. The PBIW Decoder experiments show that the adoption of PBIW Decoder circuit shrinks the processor total area in 15% (on average) and dynamic power reduction in 40%. In addition, the PBIW Decoder reduces 56% and 52% the dynamic power consumption and the amount of data stored (memory bits of M4K memory blocks) in the Instruction memory.
Michio Yokoyama - One of the best experts on this subject based on the ideXlab platform.
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Design of a 16-bit Non-pipelined RISC CPU in a Two Phase Drive Adiabatic Dynamic CMOS Logic
International Journal of Computer and Electrical Engineering, 2009Co-Authors: Yasuhiro Takahashi, Toshikazu Sekine, Michio YokoyamaAbstract:We propose a design of a 16-bit RISC CPU core using an adiabatic logic which is called a two phase drive adiabatic dynamic CMOS logic (2PADCL), in this paper. The proposed adiabatic RISC CPU is non-pipelined with a latency of three cycles, and also consists of six blocks; an arithmetic and logic unit (ALU), a program counter, a register file, an Instruction Decoder unit, a multiplexer and a clock control unit. Through the SPICE simulation, the 2PADCL CPU was evaluated for 0.35μm standard CMOS library and was compared with the CMOS CPU. The simulation results show that the power consumption of the adiabatic CPU is about 1/4 compared to that of the CMOS CPU.
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Design of a 16-bit RISC CPU core in a two phase drive adiabatic dynamic CMOS logic
TENCON 2007 - 2007 IEEE Region 10 Conference, 2007Co-Authors: Yasuhiro Takahashi, Toshikazu Sekine, D. Tsuzuki, Michio YokoyamaAbstract:We propose a design of a 16-bit RISC CPU core using an adiabatic logic which is called a two phase drive adiabatic dynamic CMOS logic (2PADCL), in this paper. The proposed adiabatic RISC CPU is non-pipelined with a latency of three cycles, and also consists of six blocks; an arithmetic and logic unit (ALU), a program counter, a register file, an Instruction Decoder unit, a multiplexer and a clock control unit. Through the SPICE simulation, the 2PADCL CPU was evaluated for 0.35 mum standard CMOS library and was compared with the CMOS CPU. The simulation results show that the power consumption of the adiabatic CPU is about 1/4 compared to that of the CMOS CPU.
A C H Wu - One of the best experts on this subject based on the ideXlab platform.
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Decomposition of Instruction Decoders for low-power designs
ACM Transactions on Design Automation of Electronic Systems, 2006Co-Authors: Tingting Hwang, A C H WuAbstract:During the execution of processor Instruction, decoding the Instructions is a major task in identifying Instructions and generating control signals for data paths. In this article, we propose two Instruction Decoder decomposition techniques for low-power designs. First, by tracing program execution sequences, we propose an algorithm that explores the relations between frequently executed Instructions. Second, we propose a two-stage low-power decomposition structure for decoding Instructions. Experimental results demonstrate that our proposed techniques achieve an average of 34.18p in power reduction and 12.93p in critical-path delay reduction for the Instruction Decoder.
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decomposition of Instruction Decoder for low power designs
International Symposium on VLSI Design Automation and Test, 2005Co-Authors: Tingting Hwang, A C H WuAbstract:During the execution of Instructions, Instruction decoding is a major task for identifying Instruction and generating control signals of data-paths. By tracing program execution sequences, the authors proposed an algorithm that exploits relations between Instructions of frequently-executed Instruction groups. After partitioning Instructions into groups, a two-stage low-power decomposition architecture was used for Instruction decoding. Experimental results have demonstrated that the proposed approach achieved an average of 29.97% and 18.94% power reductions, and 12.93% and 12.36% critical-path delay reductions for the Instruction Decoder and the control unit, respectively.
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decomposition of Instruction Decoder for low power design
Design Automation and Test in Europe, 2004Co-Authors: Tingting Hwang, A C H WuAbstract:Microprocessors have been used in wide-ranged applications. During the execution of Instructions, Instruction decoding is a major task for identifying Instructions and generating control signals for data-paths. By exploiting program behaviors, we propose a novel Instruction-decoding approach for power minimization. Using the proposed Instruction-decoding structure, we present a partitioning method that decomposes the Instruction-decoding circuit into two sub-circuits according to the execution frequencies of Instructions. Using our proposed decoding structure, only one sub-circuit will be activated when executing an Instruction. Experimental results have demonstrated that our proposed approach achieves on an average of 26.71% and 15.69% power reductions for the Instruction Decoder and the control unit, respectively.
Renan Marks - One of the best experts on this subject based on the ideXlab platform.
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SoCC - Instruction Decoders based on pattern factorization
2015 28th IEEE International System-on-Chip Conference (SOCC), 2015Co-Authors: Ricardo Santos, Renan Marks, Felipe Araújo, Rafael Alves, Renato SantosAbstract:This work presents the design of hardware Instruction Decoders based on the Pattern Based Instruction Word (PBIW) encoding technique. Instruction Decoder circuits have been designed in the datapath of ρ-VEX and the Leon3 soft-core embedded processors. The PBIW encoding scheme focuses on extracting out patterns from original Instructions at compiler time. The PBIW hardware Decoder works on the processor datapath simplifying the decoding Instruction logic by exploring the hardware parallelism between Instruction decoding and register read. The experiments show that the Instruction Decoders based on the PBIW technique present small impacts on area, dynamic power, and timing (3%–10% decrease on clock frequency) on the processor design.
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WSCAD-SSC - Design and Implementation of the PBIW Instruction Decoder in a Softcore Embedded Processor
2012 13th Symposium on Computer Systems, 2012Co-Authors: Renan Marks, Felipe Araújo, Renato Santos, Felipe Yonehara, Ricardo SantosAbstract:This paper presents the PBIW (Pattern Based Instruction Word) Instruction encoding technique on the \RVEX embedded soft core processor. The PBIW encoding technique maps the assembly generated by a compiler into an encoding scheme of a target processor. The results obtained shows that the PBIW encoding has a compression ratio ranging from 60.97% to 115.91% among the evaluated programs. The impact of PBIW encoding in the memory access shows significant performance gains since there are improvements in hit ratio up to 58.93%. The PBIW Decoder experiments show that the adoption of PBIW Decoder circuit shrinks the processor total area in 15% (on average) and dynamic power reduction in 40%. In addition, the PBIW Decoder reduces 56% and 52% the dynamic power consumption and the amount of data stored (memory bits of M4K memory blocks) in the Instruction memory.
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Design and Implementation of the PBIW Instruction Decoder in a Softcore Embedded Processor
2012 13th Symposium on Computer Systems, 2012Co-Authors: Renan Marks, Felipe Araújo, Renato Santos, Felipe Yonehara, Ricardo SantosAbstract:This paper presents the PBIW (Pattern Based Instruction Word) Instruction encoding technique on the \RVEX embedded soft core processor. The PBIW encoding technique maps the assembly generated by a compiler into an encoding scheme of a target processor. The results obtained shows that the PBIW encoding has a compression ratio ranging from 60.97% to 115.91% among the evaluated programs. The impact of PBIW encoding in the memory access shows significant performance gains since there are improvements in hit ratio up to 58.93%. The PBIW Decoder experiments show that the adoption of PBIW Decoder circuit shrinks the processor total area in 15% (on average) and dynamic power reduction in 40%. In addition, the PBIW Decoder reduces 56% and 52% the dynamic power consumption and the amount of data stored (memory bits of M4K memory blocks) in the Instruction memory.