The Experts below are selected from a list of 90171 Experts worldwide ranked by ideXlab platform
Peng Zhang - One of the best experts on this subject based on the ideXlab platform.
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An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016Co-Authors: Jason Cong, Peng Li, Bingjun Xiao, Peng ZhangAbstract:High-level synthesis (HLS) tools have made significant progress in compiling high-level descriptions of computation into highly pipelined register-transfer level specifications. The high-throughput computation raises a high data demand. To prevent data accesses from being the bottleneck, on-chip memories are used as data reuse buffers to reduce off-chip accesses. Also memory partitioning is explored to increase the memory bandwidth by scheduling multiple simultaneous memory accesses to different memory banks. Prior work on memory partitioning of data reuse buffers is limited to uniform partitioning. In this paper, we perform an early-stage exploration of nonuniform memory partitioning. We use the stencil computation, a popular communication-Intensive Application domain, as a case study to show the potential benefits of nonuniform memory partitioning. Our novel method can always achieve the minimum memory size and the minimum number of memory banks, which cannot be guaranteed in any prior work. We develop a generalized microarchitecture to decouple stencil accesses from computation, and an automated design flow to integrate our microarchitecture with the HLS-generated computation kernel for a complete accelerator.
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DAC - An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers
Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14, 2014Co-Authors: Jason Cong, Peng Li, Bingjun Xiao, Peng ZhangAbstract:High-level synthesis (HLS) tools have made significant progress in compiling high-level descriptions of computation into highly pipelined register-transfer level (RTL) specifications. The high-throughput computation raises a high data demand. To prevent data accesses from being the bottleneck, on-chip memories are used as data reuse buffers to reduce off-chip accesses. Also memory partitioning is explored to increase the memory bandwidth by scheduling multiple simultaneous memory accesses to different memory banks. Prior work on memory partitioning of data reuse buffers is limited to uniform partitioning. In this paper, we perform an early-stage exploration of non-uniform memory partitioning. We use the stencil computation, a popular communication-Intensive Application domain, as a case study to show the potential benefits of non-uniform memory partitioning. Our novel method can always achieve the minimum memory size and the minimum number of memory banks, which cannot be guaranteed in any prior work. We develop a generalized microarchitecture to decouple stencil accesses from computation, and an automated design flow to integrate our microarchitecture with the HLS-generated computation kernel for a complete accelerator.
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an optimal microarchitecture for stencil computation acceleration based on non uniform partitioning of data reuse buffers
Design Automation Conference, 2014Co-Authors: Jason Cong, Peng Li, Bingjun Xiao, Peng ZhangAbstract:High-level synthesis (HLS) tools have made significant progress in compiling high-level descriptions of computation into highly pipelined register-transfer level (RTL) specifications. The high-throughput computation raises a high data demand. To prevent data accesses from being the bottleneck, on-chip memories are used as data reuse buffers to reduce off-chip accesses. Also memory partitioning is explored to increase the memory bandwidth by scheduling multiple simultaneous memory accesses to different memory banks. Prior work on memory partitioning of data reuse buffers is limited to uniform partitioning. In this paper, we perform an early-stage exploration of non-uniform memory partitioning. We use the stencil computation, a popular communication-Intensive Application domain, as a case study to show the potential benefits of non-uniform memory partitioning. Our novel method can always achieve the minimum memory size and the minimum number of memory banks, which cannot be guaranteed in any prior work. We develop a generalized microarchitecture to decouple stencil accesses from computation, and an automated design flow to integrate our microarchitecture with the HLS-generated computation kernel for a complete accelerator.
Eduard Ayguadé - One of the best experts on this subject based on the ideXlab platform.
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spark deployment and performance evaluation on the marenostrum supercomputer
International Conference on Big Data, 2015Co-Authors: Ruben Tous, Eduard Ayguadé, Anastasios Gounaris, Carlos Tripiana, Jordi Torres, Sergi Girona, Jesus Labarta, Yolanda Becerra, David Carrera, Mateo ValeroAbstract:In this paper we present a framework to enable data-Intensive Spark workloads on MareNostrum, a petascale supercomputer designed mainly for compute-Intensive Applications. As far as we know, this is the first attempt to investigate optimized deployment configurations of Spark on a petascale HPC setup. We detail the design of the framework and present some benchmark data to provide insights into the scalabilityof the system. We examine the impact of different configurations including parallelism, storage and networking alternatives, and we discuss several aspects in executing Big Data workloads on a computing system that is based on the compute-centric paradigm. Further, we derive conclusions aiming to pave the way towards systematic and optimized methodologies for fine-tuning data-Intensive Application on large clusters emphasizing on parallelism configurations.
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ppmc a programmable pattern based memory controller
Applied Reconfigurable Computing, 2012Co-Authors: Tassadaq Hussain, Miquel Pericàs, Nacho Navarro, Muhammad Shafiq, Eduard AyguadéAbstract:One of the main challenges in the design of hardware accelerators is the efficient access of data from the external memory. Improving and optimizing the functionality of the memory controller between the external memory and the accelerators is therefore critical. In this paper, we advance toward this goal by proposing PPMC, the Programmable Pattern-based Memory Controller. This controller supports scatter-gather and strided 1D, 2D and 3D accesses with programmable tiling. Compared to existing solutions, the proposed system provides better performance, simplifies programming access patterns and eases software integration by interfacing to high-level programming languages. In addition, the controller offers an interface for automating domain decomposition via tiling. We implemented and tested PPMC on a Xilinx ML505 evaluation board using a MicroBlaze soft-core as the host processor. The evaluation uses six memory Intensive Application kernels: Laplacian solver, FIR, FFT, Thresholding, Matrix Multiplication, and 3D-Stencil. The results show that the PPMC-enhanced system achieves at least 10x speed-ups for 1D, 2D and 3D memory accesses as compared to a non-PPMC based setup.
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ARC - PPMC: a programmable pattern based memory controller
Lecture Notes in Computer Science, 2012Co-Authors: Tassadaq Hussain, Miquel Pericàs, Nacho Navarro, Muhammad Shafiq, Eduard AyguadéAbstract:One of the main challenges in the design of hardware accelerators is the efficient access of data from the external memory. Improving and optimizing the functionality of the memory controller between the external memory and the accelerators is therefore critical. In this paper, we advance toward this goal by proposing PPMC, the Programmable Pattern-based Memory Controller. This controller supports scatter-gather and strided 1D, 2D and 3D accesses with programmable tiling. Compared to existing solutions, the proposed system provides better performance, simplifies programming access patterns and eases software integration by interfacing to high-level programming languages. In addition, the controller offers an interface for automating domain decomposition via tiling. We implemented and tested PPMC on a Xilinx ML505 evaluation board using a MicroBlaze soft-core as the host processor. The evaluation uses six memory Intensive Application kernels: Laplacian solver, FIR, FFT, Thresholding, Matrix Multiplication, and 3D-Stencil. The results show that the PPMC-enhanced system achieves at least 10x speed-ups for 1D, 2D and 3D memory accesses as compared to a non-PPMC based setup.
Patrick Valduriez - One of the best experts on this subject based on the ideXlab platform.
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Distributed Caching of Scientific Workflows in Multisite Cloud
2020Co-Authors: Gaëtan Heidsieck, Daniel De Oliveira, Esther Pacitti, Christophe Pradal, Francois Tardieu, Patrick ValduriezAbstract:Many scientific experiments are performed using scientific workflows, which are becoming more and more data-Intensive. We consider the efficient execution of such workflows in the cloud, leveraging the heterogeneous resources available at multiple cloud sites (geo-distributed data centers). Since it is common for workflow users to reuse code or data from other workflows, a promising approach for efficient workflow execution is to cache intermediate data in order to avoid re-executing entire workflows. In this paper, we propose a solution for distributed caching of scientific workflows in a multisite cloud. We implemented our solution in the OpenAlea workflow system, together with cache-aware distributed scheduling algorithms. Our experimental evaluation on a three-site cloud with a data-Intensive Application in plant phenotyping shows that our solution can yield major performance gains, reducing total time up to 42% with 60% of same input data for each new execution.
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Efficient Execution of Scientific Workflows in the Cloud Through Adaptive Caching
Transactions on Large-Scale Data- and Knowledge-Centered Systems, 2020Co-Authors: Gaëtan Heidsieck, Daniel De Oliveira, Esther Pacitti, Christophe Pradal, Francois Tardieu, Patrick ValduriezAbstract:Many scientific experiments are now carried on using scientific workflows, which are becoming more and more data-Intensive and complex. We consider the efficient execution of such workflows in the cloud. Since it is common for workflow users to reuse other workflows or data generated by other workflows, a promising approach for efficient workflow execution is to cache intermediate data and exploit it to avoid task re-execution. In this paper, we propose an adaptive caching solution for data-Intensive workflows in the cloud. Our solution is based on a new scientific workflow management architecture that automatically manages the storage and reuse of intermediate data and adapts to the variations in task execution times and output data size. We evaluated our solution by implementing it in the OpenAlea system and performing extensive experiments on real data with a data-Intensive Application in plant phenotyping. The results show that adaptive caching can yield major performance gains, e.g., up to a factor of 3.5 with 6 workflow re-executions.
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Adaptive Caching for Data-Intensive Scientific Workflows in the Cloud
2019Co-Authors: Gaëtan Heidsieck, Daniel De Oliveira, Esther Pacitti, Christophe Pradal, Francois Tardieu, Patrick ValduriezAbstract:Many scientific experiments are now carried on using scien-tific workflows, which are becoming more and more data-Intensive and complex. We consider the efficient execution of such workflows in the cloud. Since it is common for workflow users to reuse other workflows or data generated by other workflows, a promising approach for efficient workflow execution is to cache intermediate data and exploit it to avoid task re-execution. In this paper, we propose an adaptive caching solution for data-Intensive workflows in the cloud. Our solution is based on a new scientific workflow management architecture that automatically manages the storage and reuse of intermediate data and adapts to the variations in task execution times and output data size. We evaluated our solution by implementing it in the OpenAlea system and performing extensive experiments on real data with a data-Intensive Application inplant phenotyping. The results show that adaptive caching can yield major performance gains,e.g., up to 120.16% with 6 workflow re-executions.
Jason Cong - One of the best experts on this subject based on the ideXlab platform.
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An Optimal Microarchitecture for Stencil Computation Acceleration Based on Nonuniform Partitioning of Data Reuse Buffers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2016Co-Authors: Jason Cong, Peng Li, Bingjun Xiao, Peng ZhangAbstract:High-level synthesis (HLS) tools have made significant progress in compiling high-level descriptions of computation into highly pipelined register-transfer level specifications. The high-throughput computation raises a high data demand. To prevent data accesses from being the bottleneck, on-chip memories are used as data reuse buffers to reduce off-chip accesses. Also memory partitioning is explored to increase the memory bandwidth by scheduling multiple simultaneous memory accesses to different memory banks. Prior work on memory partitioning of data reuse buffers is limited to uniform partitioning. In this paper, we perform an early-stage exploration of nonuniform memory partitioning. We use the stencil computation, a popular communication-Intensive Application domain, as a case study to show the potential benefits of nonuniform memory partitioning. Our novel method can always achieve the minimum memory size and the minimum number of memory banks, which cannot be guaranteed in any prior work. We develop a generalized microarchitecture to decouple stencil accesses from computation, and an automated design flow to integrate our microarchitecture with the HLS-generated computation kernel for a complete accelerator.
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DAC - An Optimal Microarchitecture for Stencil Computation Acceleration Based on Non-Uniform Partitioning of Data Reuse Buffers
Proceedings of the The 51st Annual Design Automation Conference on Design Automation Conference - DAC '14, 2014Co-Authors: Jason Cong, Peng Li, Bingjun Xiao, Peng ZhangAbstract:High-level synthesis (HLS) tools have made significant progress in compiling high-level descriptions of computation into highly pipelined register-transfer level (RTL) specifications. The high-throughput computation raises a high data demand. To prevent data accesses from being the bottleneck, on-chip memories are used as data reuse buffers to reduce off-chip accesses. Also memory partitioning is explored to increase the memory bandwidth by scheduling multiple simultaneous memory accesses to different memory banks. Prior work on memory partitioning of data reuse buffers is limited to uniform partitioning. In this paper, we perform an early-stage exploration of non-uniform memory partitioning. We use the stencil computation, a popular communication-Intensive Application domain, as a case study to show the potential benefits of non-uniform memory partitioning. Our novel method can always achieve the minimum memory size and the minimum number of memory banks, which cannot be guaranteed in any prior work. We develop a generalized microarchitecture to decouple stencil accesses from computation, and an automated design flow to integrate our microarchitecture with the HLS-generated computation kernel for a complete accelerator.
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an optimal microarchitecture for stencil computation acceleration based on non uniform partitioning of data reuse buffers
Design Automation Conference, 2014Co-Authors: Jason Cong, Peng Li, Bingjun Xiao, Peng ZhangAbstract:High-level synthesis (HLS) tools have made significant progress in compiling high-level descriptions of computation into highly pipelined register-transfer level (RTL) specifications. The high-throughput computation raises a high data demand. To prevent data accesses from being the bottleneck, on-chip memories are used as data reuse buffers to reduce off-chip accesses. Also memory partitioning is explored to increase the memory bandwidth by scheduling multiple simultaneous memory accesses to different memory banks. Prior work on memory partitioning of data reuse buffers is limited to uniform partitioning. In this paper, we perform an early-stage exploration of non-uniform memory partitioning. We use the stencil computation, a popular communication-Intensive Application domain, as a case study to show the potential benefits of non-uniform memory partitioning. Our novel method can always achieve the minimum memory size and the minimum number of memory banks, which cannot be guaranteed in any prior work. We develop a generalized microarchitecture to decouple stencil accesses from computation, and an automated design flow to integrate our microarchitecture with the HLS-generated computation kernel for a complete accelerator.
Fernando Teixeira Nicoloso - One of the best experts on this subject based on the ideXlab platform.
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triggered antioxidant defense mechanism in maize grown in soil with accumulation of cu and zn due to Intensive Application of pig slurry
Ecotoxicology and Environmental Safety, 2013Co-Authors: Eduardo Girotto, Carlos Alberto Ceretta, Liana Veronica Rossato, Julia Gomes Farias, Tadeu Luis Tiecher, Lessandro De Conti, Roberta Schmatz, Gustavo Brunetto, Maria Rosa Chitolina Schetinger, Fernando Teixeira NicolosoAbstract:The present study investigated changes in both the growth parameters and the enzymatic and non-enzymatic antioxidant systems of maize (Zea may L.) plants grown in Typic Hapludalf soil containing an accumulation of Cu and Zn. This accumulation developed because the soil received nineteen Applications of pig slurry in no-tillage system over seven years. In this study, the maize plants were grown for fifteen and 25 days after emergence (DAE) in pots containing undisturbed and disturbed soil samples collected from a field experiment that received the rates 0, 20, 40 and 80m(3)ha(-1) of pig slurry, which totalized the amount of 0, 380, 760 and 1520m(3)ha(-1) of pig slurry in seven years, respectively, and phosphorus (P)+potassium (K) treatment (in disturbed soil samples). The maize plants grown in the undisturbed soil samples with an accumulation of Cu and Zn did not indicate an apparent decrease in growth. However, when compared to the treatment with PK fertilization, the maize plants grown in the disturbed soil with pig slurry treatments indicated higher lipid peroxidation and a number of senescent leaves, as well as a significant decrease in plant height. Additionally, when compared to the PK treatment, the leaf superoxide dismutase and ascorbate peroxidase activities decreased and increased, respectively, with the addition of pig slurry treatments in the disturbed soil at 25 DAE. In general, when compared to the treatments with 20m(3)ha(-1) of pig slurry and PK at fifteen and 25 DAE, the leaf ascorbic acid and non-protein thiol groups concentrations decreased with the addition of 40 and 80m(3)ha(-1) of pig slurry. This result suggests that the excess of Cu and Zn in the pig slurry significantly changed the antioxidant system of the maize plants.