The Experts below are selected from a list of 270 Experts worldwide ranked by ideXlab platform
Chao Wang - One of the best experts on this subject based on the ideXlab platform.
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ASE - Modular verification of Interrupt-driven software
2017 32nd IEEE ACM International Conference on Automated Software Engineering (ASE), 2017Co-Authors: Chungha Sung, Markus Kusano, Chao WangAbstract:Interrupts have been widely used in safety-critical computer systems to handle outside stimuli and interact with the hardware, but reasoning about Interrupt-driven software remains a difficult task. Although a number of static verification techniques have been proposed for Interrupt-driven software, they often rely on constructing a monolithic verification model. Furthermore, they do not precisely capture the complete execution semantics of Interrupts such as nested invocations of Interrupt Handlers. To overcome these limitations, we propose an abstract interpretation framework for static verification of Interrupt-driven software that first analyzes each Interrupt Handler in isolation as if it were a sequential program, and then propagates the result to other Interrupt Handlers. This iterative process continues until results from all Interrupt Handlers reach a fixed point. Since our method never constructs the global model, it avoids the up-front blowup in model construction that hampers existing, non-modular, verification techniques. We have evaluated our method on 35 Interrupt-driven applications with a total of 22,541 lines of code. Our results show the method is able to quickly and more accurately analyze the behavior of Interrupts.
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Modular verification of Interrupt-driven software
2017 32nd IEEE ACM International Conference on Automated Software Engineering (ASE), 2017Co-Authors: Chungha Sung, Markus Kusano, Chao WangAbstract:Interrupts have been widely used in safety-critical computer systems to handle outside stimuli and interact with the hardware, but reasoning about Interrupt-driven software remains a difficult task. Although a number of static verification techniques have been proposed for Interrupt-driven software, they often rely on constructing a monolithic verification model. Furthermore, they do not precisely capture the complete execution semantics of Interrupts such as nested invocations of Interrupt Handlers. To overcome these limitations, we propose an abstract interpretation framework for static verification of Interrupt-driven software that first analyzes each Interrupt Handler in isolation as if it were a sequential program, and then propagates the result to other Interrupt Handlers. This iterative process continues until results from all Interrupt Handlers reach a fixed point. Since our method never constructs the global model, it avoids the up-front blowup in model construction that hampers existing, non-modular, verification techniques. We have evaluated our method on 35 Interrupt-driven applications with a total of 22,541 lines of code. Our results show the method is able to quickly and more accurately analyze the behavior of Interrupts.
C. Mello - One of the best experts on this subject based on the ideXlab platform.
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SBAC-PAD - A time Petri net-based approach for software synthesis considering overheads
17th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'05), 2005Co-Authors: R. Barreto, E. Tavares, P. Maciel, M. Oliveira, R. Lima, Layane Valéria Amorim, C.u.s. Carvalho, C. MelloAbstract:The context of this work is related to embedded hard real-time systems development, more specifically, in the software generation phase. Embedded software has become much harder to design caused by the diversity of requirements and high complexity. Correctness and timeliness verification is an issue to be concerned. Usually, complex embedded real-time systems rely on specialized operating system kernels. However, operating systems may introduce significant overheads in execution time as well as in memory requirement. Software synthesis might be an alternative approach to operating systems usage, since it can generate tailored code for satisfying functional, performance, and resource constraints, and automatically generate runtime support (scheduling, resource management, communication, etc.) customized for each particular specification. However, the dispatcher and timer Interrupt Handler overheads are often neglect in software synthesis research. This paper provides a formal approach for system's modeling, and such model is adopted for synthesizing a timely and predictable scheduled code taking into account dispatcher and Interrupt Handler overheads.
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A time Petri net-based approach for software synthesis considering overheads
17th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'05), 2005Co-Authors: R. Barreto, E. Tavares, P. Maciel, M. Oliveira, L. Amorim, R. Lima, C. Carvalho, C. MelloAbstract:The context of this work is related to embedded hard real-time systems development, more specifically, in the software generation phase. Embedded software has become much harder to design caused by the diversity of requirements and high complexity. Correctness and timeliness verification is an issue to be concerned. Usually, complex embedded real-time systems rely on specialized operating system kernels. However, operating systems may introduce significant overheads in execution time as well as in memory requirement. Software synthesis might be an alternative approach to operating systems usage, since it can generate tailored code for satisfying functional, performance, and resource constraints, and automatically generate runtime support (scheduling, resource management, communication, etc.) customized for each particular specification. However, the dispatcher and timer Interrupt Handler overheads are often neglect in software synthesis research. This paper provides a formal approach for system's modeling, and such model is adopted for synthesizing a timely and predictable scheduled code taking into account dispatcher and Interrupt Handler overheads.
R.a. Walker - One of the best experts on this subject based on the ideXlab platform.
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Interrupt Triggered Software Prefetching for Embedded CPU Instruction Cache
12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06), 2006Co-Authors: K.w. Batcher, R.a. WalkerAbstract:In embedded systems, handling time-critical real-time tasks is a challenge. The software may not only multi-task to improve response time, but also support events and Interrupts, forcing the system to balance multiple priorities. Further, pre-emptive task switching hampers efficient Interrupt processing, leading to instruction cache misses. This research provides a methodology for using software prefetch instructions in the Interrupt Handler to improve efficiency, thus making instruction caches more attractive in a real-time environment. The benefits of this technique are illustrated on an ARM processor running application benchmarks with different cache configurations and Interrupt arrival patterns.
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IEEE Real Time Technology and Applications Symposium - Interrupt Triggered Software Prefetching for Embedded CPU Instruction Cache
12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06), 2006Co-Authors: K.w. Batcher, R.a. WalkerAbstract:In embedded systems, handling time-critical real-time tasks is a challenge. The software may not only multi-task to improve response time, but also support events and Interrupts, forcing the system to balance multiple priorities. Further, pre-emptive task switching hampers efficient Interrupt processing, leading to instruction cache misses. This research provides a methodology for using software prefetch instructions in the Interrupt Handler to improve efficiency, thus making instruction caches more attractive in a real-time environment. The benefits of this technique are illustrated on an ARM processor running application benchmarks with different cache configurations and Interrupt arrival patterns.
Chungha Sung - One of the best experts on this subject based on the ideXlab platform.
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ASE - Modular verification of Interrupt-driven software
2017 32nd IEEE ACM International Conference on Automated Software Engineering (ASE), 2017Co-Authors: Chungha Sung, Markus Kusano, Chao WangAbstract:Interrupts have been widely used in safety-critical computer systems to handle outside stimuli and interact with the hardware, but reasoning about Interrupt-driven software remains a difficult task. Although a number of static verification techniques have been proposed for Interrupt-driven software, they often rely on constructing a monolithic verification model. Furthermore, they do not precisely capture the complete execution semantics of Interrupts such as nested invocations of Interrupt Handlers. To overcome these limitations, we propose an abstract interpretation framework for static verification of Interrupt-driven software that first analyzes each Interrupt Handler in isolation as if it were a sequential program, and then propagates the result to other Interrupt Handlers. This iterative process continues until results from all Interrupt Handlers reach a fixed point. Since our method never constructs the global model, it avoids the up-front blowup in model construction that hampers existing, non-modular, verification techniques. We have evaluated our method on 35 Interrupt-driven applications with a total of 22,541 lines of code. Our results show the method is able to quickly and more accurately analyze the behavior of Interrupts.
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Modular verification of Interrupt-driven software
2017 32nd IEEE ACM International Conference on Automated Software Engineering (ASE), 2017Co-Authors: Chungha Sung, Markus Kusano, Chao WangAbstract:Interrupts have been widely used in safety-critical computer systems to handle outside stimuli and interact with the hardware, but reasoning about Interrupt-driven software remains a difficult task. Although a number of static verification techniques have been proposed for Interrupt-driven software, they often rely on constructing a monolithic verification model. Furthermore, they do not precisely capture the complete execution semantics of Interrupts such as nested invocations of Interrupt Handlers. To overcome these limitations, we propose an abstract interpretation framework for static verification of Interrupt-driven software that first analyzes each Interrupt Handler in isolation as if it were a sequential program, and then propagates the result to other Interrupt Handlers. This iterative process continues until results from all Interrupt Handlers reach a fixed point. Since our method never constructs the global model, it avoids the up-front blowup in model construction that hampers existing, non-modular, verification techniques. We have evaluated our method on 35 Interrupt-driven applications with a total of 22,541 lines of code. Our results show the method is able to quickly and more accurately analyze the behavior of Interrupts.
R. Barreto - One of the best experts on this subject based on the ideXlab platform.
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SBAC-PAD - A time Petri net-based approach for software synthesis considering overheads
17th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'05), 2005Co-Authors: R. Barreto, E. Tavares, P. Maciel, M. Oliveira, R. Lima, Layane Valéria Amorim, C.u.s. Carvalho, C. MelloAbstract:The context of this work is related to embedded hard real-time systems development, more specifically, in the software generation phase. Embedded software has become much harder to design caused by the diversity of requirements and high complexity. Correctness and timeliness verification is an issue to be concerned. Usually, complex embedded real-time systems rely on specialized operating system kernels. However, operating systems may introduce significant overheads in execution time as well as in memory requirement. Software synthesis might be an alternative approach to operating systems usage, since it can generate tailored code for satisfying functional, performance, and resource constraints, and automatically generate runtime support (scheduling, resource management, communication, etc.) customized for each particular specification. However, the dispatcher and timer Interrupt Handler overheads are often neglect in software synthesis research. This paper provides a formal approach for system's modeling, and such model is adopted for synthesizing a timely and predictable scheduled code taking into account dispatcher and Interrupt Handler overheads.
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A time Petri net-based approach for software synthesis considering overheads
17th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD'05), 2005Co-Authors: R. Barreto, E. Tavares, P. Maciel, M. Oliveira, L. Amorim, R. Lima, C. Carvalho, C. MelloAbstract:The context of this work is related to embedded hard real-time systems development, more specifically, in the software generation phase. Embedded software has become much harder to design caused by the diversity of requirements and high complexity. Correctness and timeliness verification is an issue to be concerned. Usually, complex embedded real-time systems rely on specialized operating system kernels. However, operating systems may introduce significant overheads in execution time as well as in memory requirement. Software synthesis might be an alternative approach to operating systems usage, since it can generate tailored code for satisfying functional, performance, and resource constraints, and automatically generate runtime support (scheduling, resource management, communication, etc.) customized for each particular specification. However, the dispatcher and timer Interrupt Handler overheads are often neglect in software synthesis research. This paper provides a formal approach for system's modeling, and such model is adopted for synthesizing a timely and predictable scheduled code taking into account dispatcher and Interrupt Handler overheads.
