Interrupted Program

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Jifeng He - One of the best experts on this subject based on the ideXlab platform.

  • ICECCS - Probabilistic Denotational Semantics for an Interrupt Modelling Language
    2015 20th International Conference on Engineering of Complex Computer Systems (ICECCS), 2015
    Co-Authors: Yanhong Huang, Yongxin Zhao, Jifeng He
    Abstract:

    Interrupts play an important role in real time and embedded systems. It is purposely designed to handle unexpected and emergent issues. However, the randomicity of interrupts brings some potential safety problems, i.e., too frequently interrupt handling would cause the Interrupted Program to miss its deadline. It is therefore difficult to precisely predict and formally reason about a Program's behavior in the presence of interrupts. In this paper, we move one step forward by proposing a probabilistic denotational model for an interrupt modeling language that is capable of describing Programs with nested interrupts, to characterise the formal semantics of such Programs from a quantitative perspective under Hoare and He's UTP framework. On top of the denotational model, we also present a set of algebraic laws involving distinct features. Our model sets up a semantic foundation for the analysis and reasoning about Programs with nested interrupts for embedded systems.

  • Probabilistic Denotational Semantics for an Interrupt Modelling Language
    2015 20th International Conference on Engineering of Complex Computer Systems (ICECCS), 2015
    Co-Authors: Yanhong Huang, Yongxin Zhao, Jifeng He
    Abstract:

    Interrupts play an important role in real time and embedded systems. It is purposely designed to handle unexpected and emergent issues. However, the randomicity of interrupts brings some potential safety problems, i.e., too frequently interrupt handling would cause the Interrupted Program to miss its deadline. It is therefore difficult to precisely predict and formally reason about a Program's behavior in the presence of interrupts. In this paper, we move one step forward by proposing a probabilistic denotational model for an interrupt modeling language that is capable of describing Programs with nested interrupts, to characterise the formal semantics of such Programs from a quantitative perspective under Hoare and He's UTP framework. On top of the denotational model, we also present a set of algebraic laws involving distinct features. Our model sets up a semantic foundation for the analysis and reasoning about Programs with nested interrupts for embedded systems.

Yanhong Huang - One of the best experts on this subject based on the ideXlab platform.

  • ICECCS - Probabilistic Denotational Semantics for an Interrupt Modelling Language
    2015 20th International Conference on Engineering of Complex Computer Systems (ICECCS), 2015
    Co-Authors: Yanhong Huang, Yongxin Zhao, Jifeng He
    Abstract:

    Interrupts play an important role in real time and embedded systems. It is purposely designed to handle unexpected and emergent issues. However, the randomicity of interrupts brings some potential safety problems, i.e., too frequently interrupt handling would cause the Interrupted Program to miss its deadline. It is therefore difficult to precisely predict and formally reason about a Program's behavior in the presence of interrupts. In this paper, we move one step forward by proposing a probabilistic denotational model for an interrupt modeling language that is capable of describing Programs with nested interrupts, to characterise the formal semantics of such Programs from a quantitative perspective under Hoare and He's UTP framework. On top of the denotational model, we also present a set of algebraic laws involving distinct features. Our model sets up a semantic foundation for the analysis and reasoning about Programs with nested interrupts for embedded systems.

  • Probabilistic Denotational Semantics for an Interrupt Modelling Language
    2015 20th International Conference on Engineering of Complex Computer Systems (ICECCS), 2015
    Co-Authors: Yanhong Huang, Yongxin Zhao, Jifeng He
    Abstract:

    Interrupts play an important role in real time and embedded systems. It is purposely designed to handle unexpected and emergent issues. However, the randomicity of interrupts brings some potential safety problems, i.e., too frequently interrupt handling would cause the Interrupted Program to miss its deadline. It is therefore difficult to precisely predict and formally reason about a Program's behavior in the presence of interrupts. In this paper, we move one step forward by proposing a probabilistic denotational model for an interrupt modeling language that is capable of describing Programs with nested interrupts, to characterise the formal semantics of such Programs from a quantitative perspective under Hoare and He's UTP framework. On top of the denotational model, we also present a set of algebraic laws involving distinct features. Our model sets up a semantic foundation for the analysis and reasoning about Programs with nested interrupts for embedded systems.

Yongxin Zhao - One of the best experts on this subject based on the ideXlab platform.

  • ICECCS - Probabilistic Denotational Semantics for an Interrupt Modelling Language
    2015 20th International Conference on Engineering of Complex Computer Systems (ICECCS), 2015
    Co-Authors: Yanhong Huang, Yongxin Zhao, Jifeng He
    Abstract:

    Interrupts play an important role in real time and embedded systems. It is purposely designed to handle unexpected and emergent issues. However, the randomicity of interrupts brings some potential safety problems, i.e., too frequently interrupt handling would cause the Interrupted Program to miss its deadline. It is therefore difficult to precisely predict and formally reason about a Program's behavior in the presence of interrupts. In this paper, we move one step forward by proposing a probabilistic denotational model for an interrupt modeling language that is capable of describing Programs with nested interrupts, to characterise the formal semantics of such Programs from a quantitative perspective under Hoare and He's UTP framework. On top of the denotational model, we also present a set of algebraic laws involving distinct features. Our model sets up a semantic foundation for the analysis and reasoning about Programs with nested interrupts for embedded systems.

  • Probabilistic Denotational Semantics for an Interrupt Modelling Language
    2015 20th International Conference on Engineering of Complex Computer Systems (ICECCS), 2015
    Co-Authors: Yanhong Huang, Yongxin Zhao, Jifeng He
    Abstract:

    Interrupts play an important role in real time and embedded systems. It is purposely designed to handle unexpected and emergent issues. However, the randomicity of interrupts brings some potential safety problems, i.e., too frequently interrupt handling would cause the Interrupted Program to miss its deadline. It is therefore difficult to precisely predict and formally reason about a Program's behavior in the presence of interrupts. In this paper, we move one step forward by proposing a probabilistic denotational model for an interrupt modeling language that is capable of describing Programs with nested interrupts, to characterise the formal semantics of such Programs from a quantitative perspective under Hoare and He's UTP framework. On top of the denotational model, we also present a set of algebraic laws involving distinct features. Our model sets up a semantic foundation for the analysis and reasoning about Programs with nested interrupts for embedded systems.

Steven Swanson - One of the best experts on this subject based on the ideXlab platform.

  • Understanding the impact of power loss on flash memory
    2011 48th ACM EDAC IEEE Design Automation Conference (DAC), 2011
    Co-Authors: Hung-wei Tseng, Laura Grupp, Steven Swanson
    Abstract:

    Flash memory is quickly becoming a common component in computer systems ranging from music players to mission-critical server systems. As flash plays a more important role, data integrity in flash memories becomes a critical question. This paper examines one aspect of that data integrity by measuring the types of errors that occur when power fails during a flash memory operation. Our findings demonstrate that power failure can lead to several non-intuitive behaviors. We find that increasing the time before power failure does not always reduce error rates and that a power failure during a Program operation can corrupt data that a previous, successful Program operation wrote to the device. Our data also show that Interrupted Program operations leave data more susceptible to read disturb and increase the probability that the Programmed data will decay over time. Finally, we show that incomplete erase operations make future Program operations to the same block unreliable.

  • DAC - Understanding the impact of power loss on flash memory
    Proceedings of the 48th Design Automation Conference on - DAC '11, 2011
    Co-Authors: Hung-wei Tseng, Laura Grupp, Steven Swanson
    Abstract:

    Flash memory is quickly becoming a common component in computer systems ranging from music players to mission-critical server systems. As flash plays a more important role, data integrity in flash memories becomes a critical question. This paper examines one aspect of that data integrity by measuring the types of errors that occur when power fails during a flash memory operation. Our findings demonstrate that power failure can lead to several non-intuitive behaviors. We find that increasing the time before power failure does not always reduce error rates and that a power failure during a Program operation can corrupt data that a previous, successful Program operation wrote to the device. Our data also show that Interrupted Program operations leave data more susceptible to read disturb and increase the probability that the Programmed data will decay over time. Finally, we show that incomplete erase operations make future Program operations to the same block unreliable.

Hung-wei Tseng - One of the best experts on this subject based on the ideXlab platform.

  • Understanding the impact of power loss on flash memory
    2011 48th ACM EDAC IEEE Design Automation Conference (DAC), 2011
    Co-Authors: Hung-wei Tseng, Laura Grupp, Steven Swanson
    Abstract:

    Flash memory is quickly becoming a common component in computer systems ranging from music players to mission-critical server systems. As flash plays a more important role, data integrity in flash memories becomes a critical question. This paper examines one aspect of that data integrity by measuring the types of errors that occur when power fails during a flash memory operation. Our findings demonstrate that power failure can lead to several non-intuitive behaviors. We find that increasing the time before power failure does not always reduce error rates and that a power failure during a Program operation can corrupt data that a previous, successful Program operation wrote to the device. Our data also show that Interrupted Program operations leave data more susceptible to read disturb and increase the probability that the Programmed data will decay over time. Finally, we show that incomplete erase operations make future Program operations to the same block unreliable.

  • DAC - Understanding the impact of power loss on flash memory
    Proceedings of the 48th Design Automation Conference on - DAC '11, 2011
    Co-Authors: Hung-wei Tseng, Laura Grupp, Steven Swanson
    Abstract:

    Flash memory is quickly becoming a common component in computer systems ranging from music players to mission-critical server systems. As flash plays a more important role, data integrity in flash memories becomes a critical question. This paper examines one aspect of that data integrity by measuring the types of errors that occur when power fails during a flash memory operation. Our findings demonstrate that power failure can lead to several non-intuitive behaviors. We find that increasing the time before power failure does not always reduce error rates and that a power failure during a Program operation can corrupt data that a previous, successful Program operation wrote to the device. Our data also show that Interrupted Program operations leave data more susceptible to read disturb and increase the probability that the Programmed data will decay over time. Finally, we show that incomplete erase operations make future Program operations to the same block unreliable.