The Experts below are selected from a list of 27144 Experts worldwide ranked by ideXlab platform
Eyee Hyun Nam - One of the best experts on this subject based on the ideXlab platform.
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CASES - Hardware/software architecture for Flash Memory storage systems
Proceedings of the 14th international conference on Compilers architectures and synthesis for embedded systems - CASES '11, 2011Co-Authors: Sang Lyul Min, Eyee Hyun NamAbstract:This tutorial deals with various hardware/software issues in designing and implementing Flash Memory storage systems. It will be split into three parts - the first part is on Flash Memory internals and Flash Memory management software called the Flash translation layer, the second on solid state disks that emulate hard disk drives using Flash Memory, and finally the third on reliability issues arising from various asynchronous/synchronous faults.
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current trends in Flash Memory technology invited paper
Asia and South Pacific Design Automation Conference, 2006Co-Authors: Sang Lyul Min, Eyee Hyun NamAbstract:In this paper, we describe the basics of Flash Memory technology in general and Flash Memory drive in particular, and explain the current trends of major components of a Flash Memory drive including Flash Memory chips, host interface and Flash Memory controller.
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ASP-DAC - Current trends in Flash Memory technology: invited paper
Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06, 2006Co-Authors: Sang Lyul Min, Eyee Hyun NamAbstract:In this paper, we describe the basics of Flash Memory technology in general and Flash Memory drive in particular, and explain the current trends of major components of a Flash Memory drive including Flash Memory chips, host interface and Flash Memory controller.
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Current trends in Flash Memory technology
Asia and South Pacific Conference on Design Automation 2006., 1Co-Authors: Sang Lyul Min, Eyee Hyun NamAbstract:In this paper, we describe the basics of Flash Memory technology in general and Flash Memory drive in particular, and explain the current trends of major components of a Flash Memory drive including Flash Memory chips, host interface and Flash Memory controller.
Lanrong Dung - One of the best experts on this subject based on the ideXlab platform.
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a nand Flash Memory controller for sd mmc Flash Memory card
IEEE Transactions on Magnetics, 2007Co-Authors: Lanrong DungAbstract:In this paper, a novel NAND Flash Memory controller was designed. A t-EC w-bit parallel Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC) was designed for correcting the random bit errors of the Flash Memory chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND-type Flash Memory. A code-banking mechanism was designed for the tradeoffs between the controller cost and the in-system programmability (ISP) support. With the ISP functionality and the Flash parameters programmed in the reserved area of the Flash Memory chip during the card production stage, the function for supporting various kinds of NAND Flash Memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual channel accessing of the Flash Memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real secure digital card (SD)/multimedia card (MMC) Flash Memory card controller chip was designed and implemented with UMC 0.18 mum CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances
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a nand Flash Memory controller for sd mmc Flash Memory card
IEEE Transactions on Magnetics, 2007Co-Authors: Lanrong DungAbstract:In this paper, a novel NAND Flash Memory controller was designed. A t-EC w-bit parallel Bose-Chaudhuri-Hocquengham (BCH) error-correction code (ECC) was designed for correcting the random bit errors of the Flash Memory chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND-type Flash Memory. A code-banking mechanism was designed for the tradeoffs between the controller cost and the in-system programmability (ISP) support. With the ISP functionality and the Flash parameters programmed in the reserved area of the Flash Memory chip during the card production stage, the function for supporting various kinds of NAND Flash Memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual channel accessing of the Flash Memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real secure digital card (SD)/multimedia card (MMC) Flash Memory card controller chip was designed and implemented with UMC 0.18 mum CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances
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ICECS - A NAND Flash Memory Controller for SD/MMC Flash Memory Card
2006 13th IEEE International Conference on Electronics Circuits and Systems, 2006Co-Authors: Chuan-sheng Lin, Kuang-yuan Chen, Yu-hsian Wang, Lanrong DungAbstract:In this paper, a novel NAND Flash Memory Controller was designed. A t-EC w-bit parallel BCH ECC code was designed for correcting the random bit errors of the Flash Memory chip, which is suitable for the randomly bit errors property and parallel I/O interface of the NAND type Flash Memory. A Code-Banking mechanism was designed for the trade-offs between the controller cost and the ISP (in system programmability) support. With the ISP functionality and the Flash Parameters programmed in the reserved area of the Flash Memory chip during the card production stage, the function for supporting various kinds of NAND Flash Memory could be provided by a single controller. In addition, built-in defect management and wear-leveling algorithm enhanced the product life cycle and reliability. Dual Channel accessing of the Flash Memory provided the good performance in data transfer rate. With respect to the proposed controller architecture, a real SD/MMC Flash Memory card controller chip was designed and implemented with UMC 0.18mum CMOS process. Experimental results show the designed circuit can fully comply with the system specifications and shows the good performances.
Tei-wei Kuo - One of the best experts on this subject based on the ideXlab platform.
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Disturbance Relaxation for 3D Flash Memory
IEEE Transactions on Computers, 2016Co-Authors: Yu-ming Chang, Yuan-hao Chang, Tei-wei KuoAbstract:Even though 3D Flash Memory presents a grand opportunity to huge-capacity non-volatile Memory, it suffers from serious program disturbance problems. In contrast to the past efforts in error correction codes and the work in trading the space utilization for reliability, we propose a disturbance-relaxation scheme that can alleviate the negative effects caused by program disturbance inside a physical block. This scheme does not introduce any extra overheads on encoding or storing of extra redundant data. In particular, a methodology is proposed to reduce the data error rate by distributing unavoidable disturbance errors to the Flash-Memory space of invalid data, with the considerations of the physical organization of 3D Flash Memory. A series of experiments was conducted based on real multi-layer 3D Flash chips, and it showed that the proposed scheme could significantly enhance the reliability of 3D Flash Memory.
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SMARTCOMP - Garbage collection and wear leveling for Flash Memory: Past and future
2014 International Conference on Smart Computing, 2014Co-Authors: Ming-chang Yang, Pochun Huang, Yuan-hao Chang, Yu-ming Chang, Che-wei Tsao, Tei-wei KuoAbstract:Recently, storage systems have observed a great leap in performance, reliability, endurance, and cost, due to the advance in non-volatile Memory technologies, such as NAND Flash Memory. However, although delivering better performance, shock resistance, and energy efficiency than mechanical hard disks, NAND Flash Memory comes with unique characteristics and operational constraints, and cannot be directly used as an ideal block device. In particular, to address the notorious write-once property, garbage collection is necessary to clean the outdated data on Flash Memory. However, garbage collection is very time-consuming and often becomes the performance bottleneck of Flash Memory. Moreover, because Flash Memory cells endure very limited writes (as compared to mechanical hard disks) before they are worn out, the wear-leveling design is also indispensable to equalize the use of Flash Memory space and to prolong the Flash Memory lifetime. In response, this paper surveys state-of-the-art garbage collection and wear-leveling designs, so as to assist the design of Flash Memory management in various application scenarios. The future development trends of Flash Memory, such as the widespread adoption of higher-level Flash Memory and the emerging of three-dimensional (3D) Flash Memory architectures, are also discussed.
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an efficient b tree layer implementation for Flash Memory storage systems
ACM Transactions in Embedded Computing Systems, 2007Co-Authors: Tei-wei Kuo, Li Ping ChangAbstract:With the significant growth of the markets for consumer electronics and various embedded systems, Flash Memory is now an economic solution for storage systems design. Because index structures require intensively fine-grained updates/modifications, block-oriented access over Flash Memory could introduce a significant number of redundant writes. This might not only severely degrade the overall performance, but also damage the reliability of Flash Memory. In this paper, we propose a very different approach, which can efficiently handle fine-grained updates/modifications caused by B-tree index access over Flash Memory. The implementation is done directly over the Flash translation layer (FTL); hence, no modifications to existing application systems are needed. We demonstrate that when index structures are adopted over Flash Memory, the proposed methodology can significantly improve the system performance and, at the same time, reduce both the overhead of Flash-Memory management and the energy dissipation. The average response time of record insertions and deletions was also significantly reduced.
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an efficient management scheme for large scale Flash Memory storage systems
ACM Symposium on Applied Computing, 2004Co-Authors: Lipin Chang, Tei-wei KuoAbstract:Flash Memory is among the top choices for storage media in ubiquitous computing. With a strong demand of high-capacity storage devices, the usages of Flash Memory quickly grow beyond their original designs. The very distinct characteristics of Flash Memory introduce serious challenges to engineers in resolving the quick degradation of system performance and the huge demand of main-Memory space for Flash-Memory management when high-capacity Flash Memory is considered. Although some brute-force solutions could be taken, such as the enlarging of management granularity for Flash Memory, we showed that little advantage is received when system performance is considered. This paper proposes a flexible management scheme for large-scale Flash-Memory storage systems. The objective is to efficiently manage high-capacity Flash-Memory storage systems based on the behaviors of realistic access patterns. The proposed scheme could significantly reduce the main-Memory usages without noticeable performance degradation.
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an efficient b tree layer for Flash Memory storage systems
Embedded and Real-Time Computing Systems and Applications, 2003Co-Authors: Lipin Chang, Tei-wei KuoAbstract:With a significant growth of the markets for consumer electronics and various embedded systems, Flash Memory is now an economic solution for storage systems design. For index structures which require intensively fine-grained updates/modifications, block-oriented access over Flash Memory could introduce a significant number of redundant writes. It might not only severely degrade the overall performance but also damage the reliability of Flash Memory. In this paper, we propose a very different approach which could efficiently handle fine-grained updates/modifications caused by B-Tree index access over Flash Memory. The implementation is done directly over the Flash translation layer (FTL) such that no modifications to existing application systems are needed. We demonstrate that the proposed methodology could significantly improve the system performance and, at the same time, reduce the overheads of Flash-Memory management and the energy dissipation, when index structures are adopted over Flash Memory.
Sang Lyul Min - One of the best experts on this subject based on the ideXlab platform.
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CASES - Hardware/software architecture for Flash Memory storage systems
Proceedings of the 14th international conference on Compilers architectures and synthesis for embedded systems - CASES '11, 2011Co-Authors: Sang Lyul Min, Eyee Hyun NamAbstract:This tutorial deals with various hardware/software issues in designing and implementing Flash Memory storage systems. It will be split into three parts - the first part is on Flash Memory internals and Flash Memory management software called the Flash translation layer, the second on solid state disks that emulate hard disk drives using Flash Memory, and finally the third on reliability issues arising from various asynchronous/synchronous faults.
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Flash Memory solid state disks
2010 International Conference on Information and Emerging Technologies, 2010Co-Authors: Sang Lyul MinAbstract:Flash Memory is increasingly being used as a storage medium for mobile devices such as mobile phones, PMPs, and UMPCs because of low power consumption, fast random access, and high shock & vibration resistance. In this talk, first I will explain the basics and current trends of NAND Flash Memory, the type of Flash Memory used for storage applications. Second, I will introduce the concept of a Flash Memory solid state disk (SSD) that provides an interface identical to that of hard disk drive (HDD) out of Flash Memory. Third, I will explain the motivations, design, implementation, and performance evaluation of the Hydra solid state disk that our research group has developed. Finally, I will conclude with future research directions on Flash Memory in general and solid state disks in particular.
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current trends in Flash Memory technology invited paper
Asia and South Pacific Design Automation Conference, 2006Co-Authors: Sang Lyul Min, Eyee Hyun NamAbstract:In this paper, we describe the basics of Flash Memory technology in general and Flash Memory drive in particular, and explain the current trends of major components of a Flash Memory drive including Flash Memory chips, host interface and Flash Memory controller.
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ASP-DAC - Current trends in Flash Memory technology: invited paper
Proceedings of the 2006 conference on Asia South Pacific design automation - ASP-DAC '06, 2006Co-Authors: Sang Lyul Min, Eyee Hyun NamAbstract:In this paper, we describe the basics of Flash Memory technology in general and Flash Memory drive in particular, and explain the current trends of major components of a Flash Memory drive including Flash Memory chips, host interface and Flash Memory controller.
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Current trends in Flash Memory technology
Asia and South Pacific Conference on Design Automation 2006., 1Co-Authors: Sang Lyul Min, Eyee Hyun NamAbstract:In this paper, we describe the basics of Flash Memory technology in general and Flash Memory drive in particular, and explain the current trends of major components of a Flash Memory drive including Flash Memory chips, host interface and Flash Memory controller.
Dongjoo Park - One of the best experts on this subject based on the ideXlab platform.
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A survey of data recovery on Flash Memory
International Journal of Electrical and Computer Engineering (IJECE), 2020Co-Authors: Van Dai Tran, Dongjoo ParkAbstract:In recent years, Flash Memory has become more widely used due to its advantages, such as fast data access, low power consumption, and high mobility. However, Flash Memory also has drawbacks that need to be overcome, such as erase-before-write, and the limitations of block deletion. In order to address this issue, the FTL (Flash Translation Layer) has been proposed with useful functionalities like address mapping, garbage collection, and wear-leveling. During the process of using, the data may be lost on power failure in the storage systems. In some systems, the data is very important. Thus recovery of data in the event of the system crash or a sudden power outage is of prime importance. This problem has attracted attention from researchers and many studies have been done. In this paper, we investigate previous studies on data recovery for Flash Memory from FTL processing solutions to PLR (Power Loss Recovery) solutions that have been proposed by authors in the conference proceeding, patents, or professional journals. This will provide a discussion of the proposed solutions to the data recovery in Flash Memory as well as an overview.
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a recovery technique against file wiping for digital forensic on nand Flash Memory
Journal of KIISE:Databases, 2012Co-Authors: Yoonbin Lim, Myungsub Shin, Dongjoo ParkAbstract:Recently, Flash Memory is used as storage system of digital devices. Anti-forensic techniques like file wiping is being tried to completely delete the stored files on Flash Memory, since they are clues in a criminal investigation. Therefore, it is necessary to develop digital forensic techniques for the analysis of digital evidence on Flash Memory to win anti-forensic techniques. Recently, data recovery approaches on Flash Memory have been proposed, which are heavily dependent of metadata stored on Flash Memory. This paper suggests a new technique to be able to recover data on Flash Memory deleted by file wiping. Differently from the previous techniques, our scheme can recovery deleted files without metadata on Flash Memory. Through diverse experiments, we show that our approach is a higher level of the data recovery technique compared with the existing techniques.
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SAC - LSTAFF*: an efficient Flash translation layer for large block Flash Memory
Proceedings of the 2011 ACM Symposium on Applied Computing - SAC '11, 2011Co-Authors: Taesun Chung, Dongjoo ParkAbstract:Recently, Flash Memory is widely used as a non-volatile storage for embedded applications such as cellular phones, mp3 players, digital cameras, and so on. The software layer called FTL (Flash translation layer) becomes more important since it is a key factor in the overall Flash Memory system performance. Many researchers have proposed FTL algorithms for small block Flash Memory in which the size of a physical page of Flash Memory is same to the size of a data sector of the file system. However, major Flash vendors have now produced large block Flash Memory in which the size of a physical page is larger than the file system's data sector size. Since large block Flash Memory has new features, designing FTL algorithms optimized for large block Flash Memory is a challenging one. In this paper, we provide an efficient FTL named LSTAFF* for large block Flash Memory. LSTAFF* is designed to achieve better performance by using characteristics of large block Flash Memory and to provide safety by abiding by restrictions of large block Flash Memory. Our experimental results show that LSTAFF* is an optimized FTL algorithm for large block Flash Memory.
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fast an efficient Flash translation layer for Flash Memory
Embedded and Ubiquitous Computing, 2006Co-Authors: Wonkyoung Choi, Dongjoo ParkAbstract:Flash Memory is used at high speed as storage of personal information utilities, ubiquitous computing environments, mobile phones, electronic goods, etc. This is because Flash Memory has the characteristics of low electronic power, non-volatile storage, high performance, physical stability, portability, and so on. However, differently from hard disks, it has a weak point that overwrites on already written block of Flash Memory is impossible to be done. In order to make it possible, an erase operation on the written block should be performed before the overwrite, which lowers the performance of Flash Memory highly. In order to solve this problem, the Flash Memory controller maintains a system software module called the Flash translation layer(FTL). In this paper, we propose an enhanced log block buffer FTL scheme, FAST(Fully Associative Sector Translation), which improves the page usability of each log block by fully associating sectors to be written by overwrites to the entire log blocks. We also show that our FAST scheme outperforms the previous log block buffer scheme.
