The Experts below are selected from a list of 33 Experts worldwide ranked by ideXlab platform
Jaijeet Roychowdhury - One of the best experts on this subject based on the ideXlab platform.
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1Rapid and Accurate Latch Characterization via Direct Newton Solution of Setup/Hold Times
2015Co-Authors: Shweta Srivastava, Jaijeet RoychowdhuryAbstract:Characterizing setup/hold times of Latches and Registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in industries such as Intel and IBM. We present a novel approach to speed up Latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation h(τ) = 0 derived using state-transition functions, and then solving this equation by Newton-Raphson (NR). The local quadratic convergence of NR results in rapid improvements in accuracy at every iteration, thereby significantly reducing the computation needed for ac-curate determination of setup/hold times. We validate the fast convergence and computational advantage of the new method on transmission gate and C2MOS Latch/Register structures, obtaining speedups of 4-10 × over the current standard of binary search. I
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Independent and Interdependent Latch Setup/Hold Time Characterization via Newton–Raphson Solution and Euler Curve Tracking of State-Transition Equations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008Co-Authors: Shweta Srivastava, Jaijeet RoychowdhuryAbstract:Characterizing setup/hold times of Latches and Registers, which is a task crucial for achieving timing closure of large digital designs, typically occupies months of computation in semiconductor industries. We present a novel approach to speed up Latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation ; this nonlinear algebraic formulation is derived from, and embeds within it, the state-transition function of the Latch. We first present a technique to characterize setup and hold times independently of each other: by decoupling into two equations and and solving each equation using the Newton-Raphson method. Next, we also present a method for interdependent characterization of Latch setup/hold times - a core component of techniques for pessimism reduction in timing analysis. We achieve this by solving the underdetermined nonlinear equation using a Moore-Penrose pseudoinverse-based Newton method. Furthermore, we use null-space information from the Newton's Jacobian matrix to efficiently find constant-clock-to- contours (in the setup/hold time plane) via an Euler-Newton curve-tracing procedure. We validate fast convergence and computational advantage for independent characterization on transmission gate and Latch/Register structures, obtaining speedups of , at high levels of accuracy, over the current standard of binary search. We validate the method for interdependent characterization on true single-phased clock and , obtaining speedups of more than 10 for tracing 17-24 points, over prior approaches while achieving superior accuracy; this speedup linearly increases with the precision with which curve tracing is desired. We also apply our method for interdependent characterization on a transmission gate Register to illustrate limitations of our method.
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DATE - Rapid and accurate Latch characterization via direct Newton solution of setup/hold times
2007 Design Automation & Test in Europe Conference & Exhibition, 2007Co-Authors: Shweta Srivastava, Jaijeet RoychowdhuryAbstract:Characterizing setup/hold times of Latches and Registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in industries such as Intel and IBM. We present a novel approach to speed up Latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation h(tau) = 0 derived using state-transition functions, and then solving this equation by Newton-Raphson (NR). The local quadratic convergence of NR results in rapid improvements in accuracy at every iteration, thereby significantly reducing the computation needed for accurate determination of setup/hold times. We validate the fast convergence and computational advantage of the new method on transmission gate and C2MOS Latch/Register structures, obtaining speedups of 4-10times over the current standard of binary search
Shweta Srivastava - One of the best experts on this subject based on the ideXlab platform.
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1Rapid and Accurate Latch Characterization via Direct Newton Solution of Setup/Hold Times
2015Co-Authors: Shweta Srivastava, Jaijeet RoychowdhuryAbstract:Characterizing setup/hold times of Latches and Registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in industries such as Intel and IBM. We present a novel approach to speed up Latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation h(τ) = 0 derived using state-transition functions, and then solving this equation by Newton-Raphson (NR). The local quadratic convergence of NR results in rapid improvements in accuracy at every iteration, thereby significantly reducing the computation needed for ac-curate determination of setup/hold times. We validate the fast convergence and computational advantage of the new method on transmission gate and C2MOS Latch/Register structures, obtaining speedups of 4-10 × over the current standard of binary search. I
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Independent and Interdependent Latch Setup/Hold Time Characterization via Newton–Raphson Solution and Euler Curve Tracking of State-Transition Equations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2008Co-Authors: Shweta Srivastava, Jaijeet RoychowdhuryAbstract:Characterizing setup/hold times of Latches and Registers, which is a task crucial for achieving timing closure of large digital designs, typically occupies months of computation in semiconductor industries. We present a novel approach to speed up Latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation ; this nonlinear algebraic formulation is derived from, and embeds within it, the state-transition function of the Latch. We first present a technique to characterize setup and hold times independently of each other: by decoupling into two equations and and solving each equation using the Newton-Raphson method. Next, we also present a method for interdependent characterization of Latch setup/hold times - a core component of techniques for pessimism reduction in timing analysis. We achieve this by solving the underdetermined nonlinear equation using a Moore-Penrose pseudoinverse-based Newton method. Furthermore, we use null-space information from the Newton's Jacobian matrix to efficiently find constant-clock-to- contours (in the setup/hold time plane) via an Euler-Newton curve-tracing procedure. We validate fast convergence and computational advantage for independent characterization on transmission gate and Latch/Register structures, obtaining speedups of , at high levels of accuracy, over the current standard of binary search. We validate the method for interdependent characterization on true single-phased clock and , obtaining speedups of more than 10 for tracing 17-24 points, over prior approaches while achieving superior accuracy; this speedup linearly increases with the precision with which curve tracing is desired. We also apply our method for interdependent characterization on a transmission gate Register to illustrate limitations of our method.
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DATE - Rapid and accurate Latch characterization via direct Newton solution of setup/hold times
2007 Design Automation & Test in Europe Conference & Exhibition, 2007Co-Authors: Shweta Srivastava, Jaijeet RoychowdhuryAbstract:Characterizing setup/hold times of Latches and Registers, a crucial component for achieving timing closure of large digital designs, typically occupies months of computation in industries such as Intel and IBM. We present a novel approach to speed up Latch characterization by formulating the setup/hold time problem as a scalar nonlinear equation h(tau) = 0 derived using state-transition functions, and then solving this equation by Newton-Raphson (NR). The local quadratic convergence of NR results in rapid improvements in accuracy at every iteration, thereby significantly reducing the computation needed for accurate determination of setup/hold times. We validate the fast convergence and computational advantage of the new method on transmission gate and C2MOS Latch/Register structures, obtaining speedups of 4-10times over the current standard of binary search
V K Semenov - One of the best experts on this subject based on the ideXlab platform.
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rsfq logic memory family a new josephson junction technology for sub terahertz clock frequency digital systems
IEEE Transactions on Applied Superconductivity, 1991Co-Authors: K K Likharev, V K SemenovAbstract:Recent developments concerning the rapid single-flux-quantum (RSFQ) circuit family are reviewed. Elementary cells in this circuit family can generate, pass, memorize, and reproduce picosecond voltage pulses with a nominally quantized area corresponding to transfer of a single magnetic flux quantum across a Josephson junction. Functionally, each cell can be viewed as a combination of a logic gate and an output Latch (Register) controlled by clock pulses, which are physically similar to the signal pulses. Hand-shaking style of local exchange by the clock pulses enables one to increase complexity of the LSI RSFQ systems without loss of operating speed. The simplest components of the RSFQ circuitry have been experimentally tested at clock frequencies exceeding 100 GHz, and an increase of the speed beyond 300 GHz is expected as a result of using an up-to-date fabrication technology. This review includes a discussion of possible future developments and applications of this novel, ultrafast digital technology. >
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RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems
IEEE Transactions on Applied Superconductivity, 1991Co-Authors: K K Likharev, V K SemenovAbstract:Recent developments concerning the rapid single-flux-quantum (RSFQ) circuit family are reviewed. Elementary cells in this circuit family can generate, pass, memorize, and reproduce picosecond voltage pulses with a nominally quantized area corresponding to transfer of a single magnetic flux quantum across a Josephson junction. Functionally, each cell can be viewed as a combination of a logic gate and an output Latch (Register) controlled by clock pulses, which are physically similar to the signal pulses. Hand-shaking style of local exchange by the clock pulses enables one to increase complexity of the LSI RSFQ systems without loss of operating speed. The simplest components of the RSFQ circuitry have been experimentally tested at clock frequencies exceeding 100 GHz, and an increase of the speed beyond 300 GHz is expected as a result of using an up-to-date fabrication technology. This review includes a discussion of possible future developments and applications of this novel, ultrafast digital technology. >
K K Likharev - One of the best experts on this subject based on the ideXlab platform.
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rsfq logic memory family a new josephson junction technology for sub terahertz clock frequency digital systems
IEEE Transactions on Applied Superconductivity, 1991Co-Authors: K K Likharev, V K SemenovAbstract:Recent developments concerning the rapid single-flux-quantum (RSFQ) circuit family are reviewed. Elementary cells in this circuit family can generate, pass, memorize, and reproduce picosecond voltage pulses with a nominally quantized area corresponding to transfer of a single magnetic flux quantum across a Josephson junction. Functionally, each cell can be viewed as a combination of a logic gate and an output Latch (Register) controlled by clock pulses, which are physically similar to the signal pulses. Hand-shaking style of local exchange by the clock pulses enables one to increase complexity of the LSI RSFQ systems without loss of operating speed. The simplest components of the RSFQ circuitry have been experimentally tested at clock frequencies exceeding 100 GHz, and an increase of the speed beyond 300 GHz is expected as a result of using an up-to-date fabrication technology. This review includes a discussion of possible future developments and applications of this novel, ultrafast digital technology. >
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RSFQ logic/memory family: a new Josephson-junction technology for sub-terahertz-clock-frequency digital systems
IEEE Transactions on Applied Superconductivity, 1991Co-Authors: K K Likharev, V K SemenovAbstract:Recent developments concerning the rapid single-flux-quantum (RSFQ) circuit family are reviewed. Elementary cells in this circuit family can generate, pass, memorize, and reproduce picosecond voltage pulses with a nominally quantized area corresponding to transfer of a single magnetic flux quantum across a Josephson junction. Functionally, each cell can be viewed as a combination of a logic gate and an output Latch (Register) controlled by clock pulses, which are physically similar to the signal pulses. Hand-shaking style of local exchange by the clock pulses enables one to increase complexity of the LSI RSFQ systems without loss of operating speed. The simplest components of the RSFQ circuitry have been experimentally tested at clock frequencies exceeding 100 GHz, and an increase of the speed beyond 300 GHz is expected as a result of using an up-to-date fabrication technology. This review includes a discussion of possible future developments and applications of this novel, ultrafast digital technology. >
Huazhong Yang - One of the best experts on this subject based on the ideXlab platform.
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A new adaptive delay method for wideband wireless Kahn's RF power amplifiers
IEEE Transactions on Consumer Electronics, 2006Co-Authors: Chuande Zhi, Huazhong YangAbstract:This paper presents an adaptive delay control method used in wideband Kahn's envelope elimination and restoration (EER) RF power amplifiers (PAs). Besides control circuits, envelope and phase signals are also implemented by baseband digital signal processing (DSP) technique. It avoids using not only nonlinear limiter and envelope detector, but also difficult RF delay module or complicated feedback loop, each of which is necessary in conventional EER PA's structure. With the help of applying phase detector, counter, and Latch Register, the delay varies adaptively with circuit parameters, and then the new PA maintains performance at all times. With the application of this method we can realize a PA applicable to IEEE 802.11b standard with 11 MHz signal bandwidth, of which adjacent channel power ratio (ACPR) is better than -40 dBc at the first side lobe
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A New Adaptive Delay Method for Wideband Kahn's RF Power Amplifiers
2006 IEEE International Symposium on Consumer Electronics, 1Co-Authors: Chuande Zhi, Huazhong YangAbstract:This paper presents an adaptive delay control method used in wideband Kahn's envelope elimination and restoration (EER) RF power amplifiers (PAs). Besides control circuits, envelope and phase signals are also implemented by baseband digital signal processing (DSP) technique. It avoids using not only nonlinear limiter and envelope detector, but also difficult RF delay module or complicated feedback loop, each of which is necessary in conventional EER PA 's structure. With the help of applying phase detector, counter, and Latch Register, the delay varies adaptively with circuit parameters, and then the new PA maintains performance at all times. With the application of this method we can realize a PA applicable to IEEE 802.11b standard with 11 MHz signal bandwidth, of which adjacent channel power ratio (ACPR) is better than -40 dBc at the first side lobe
