The Experts below are selected from a list of 3366 Experts worldwide ranked by ideXlab platform
Gaetano Palumbo - One of the best experts on this subject based on the ideXlab platform.
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Reconsidering High-Speed Design Criteria for Transmission-Gate-Based Master–Slave Flip-Flops
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2012Co-Authors: Elio Consoli, Gaetano Palumbo, Melita PennisiAbstract:In this paper we show that, when dealing with Transmission-Gate-based master-slave (TGMS) flip-flops (FFs), a reconsideration of the classical approach for the delay minimization is worthwhile to improve the performance in high-speed designs. In particular, by splitting such FFs into two sections that are separately optimized and then reconciling the results, the emerging design always outperforms the one resulting from the employment of a classical Logical Effort procedure assuming such FFs as a whole continuous path. Simulations are performed on several well-known TGMS FFs, designed in a 65-nm technology, to validate the correctness of such a procedure and of the underlying assumptions. Significant improvements are found on delay and, remarkably, on energy and area occupation, thus showing that this approach allows to correctly deal with the actual path effort in such circuits and hence to more properly steer the design towards the achievement of energy efficiency in the high-speed region.
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ICECS - Design guidelines for high-speed Transmission-Gate latches: Analysis and comparison
2008 15th IEEE International Conference on Electronics Circuits and Systems, 2008Co-Authors: Gaetano Palumbo, Melita PennisiAbstract:In this paper we present a pencil-and-paper procedure to design Transmission-Gate latches for high-speed performance. The procedure, based on the Logical Effort approach, independently optimizes the master and slave section to get minimum delay, sizing all transistors in the critical path. The other devices, like keeper transistors or switches in the positive feedback networks, are sized with minimum width thus providing only a negligible capacitive load to the internal nodes. Simulations are performed on a PowerPC 603 master-slave latch designed with a 90-nm technology provided by STMicroelectronics, and the overall good performance of the proposed procedure compared to other design strategies is verified.
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Design guidelines for high-speed Transmission-Gate latches: Analysis and comparison
2008 15th IEEE International Conference on Electronics Circuits and Systems, 2008Co-Authors: Gaetano Palumbo, Melita PennisiAbstract:In this paper we present a pencil-and-paper procedure to design Transmission-Gate latches for high-speed performance. The procedure, based on the Logical Effort approach, independently optimizes the master and slave section to get minimum delay, sizing all transistors in the critical path. The other devices, like keeper transistors or switches in the positive feedback networks, are sized with minimum width thus providing only a negligible capacitive load to the internal nodes. Simulations are performed on a PowerPC 603 master-slave latch designed with a 90-nm technology provided by STMicroelectronics, and the overall good performance of the proposed procedure compared to other design strategies is verified.
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ECCTD - Very high-speed carry computation based on mixed dynamic/Transmission-Gate Full Adders
2007 18th European Conference on Circuit Theory and Design, 2007Co-Authors: Massimo Alioto, Gaetano PalumboAbstract:In this paper, a circuit design approach to perform very fast carry computation in cascaded Full Adders is proposed. The strategy is based on the adoption of mixed dynamic and Transmission-Gate Full Adder topologies, as opposite to the traditional approach based on cascaded Full Adders based on the same logic style. Analysis shows that the insertion of Transmission-Gate Full Adders between dynamic Full Adders does not violate the timing constraints that are required by the latter ones to achieve a correct operation. To evaluate the achievable performance, the proposed approach is compared with traditional domino Full Adder chains. Post- layout simulations on a 90-nm CMOS technology show that the proposed approach outperform the domino speed performance by more than 30%, without degrading the energy efficiency and with no area penalty.
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Delay Variability Due to Supply Variations in Transmission-Gate Full Adders
2007 IEEE International Symposium on Circuits and Systems, 2007Co-Authors: Massimo Alioto, Gaetano PalumboAbstract:In this paper, the delay variability due to supply variations is investiGated for the Transmission-Gate (TG) Full Adder topology, which is well known for its very low power consumption. The delay sensitivity with respect to supply variations is first analytically modeled. The resulting model is very simple, independent of the adopted technology and useful for better understanding the delay variations due to the supply voltage fluctuations. The delay sensitivity with respect to supply variations is also compared with that of traditional CMOS Full Adders, that are frequently adopted as a reference logic style. The results are validated by means of Spectre simulations with a 90-nm and a 0.18-μm technology.
Massimo Alioto - One of the best experts on this subject based on the ideXlab platform.
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ECCTD - Very high-speed carry computation based on mixed dynamic/Transmission-Gate Full Adders
2007 18th European Conference on Circuit Theory and Design, 2007Co-Authors: Massimo Alioto, Gaetano PalumboAbstract:In this paper, a circuit design approach to perform very fast carry computation in cascaded Full Adders is proposed. The strategy is based on the adoption of mixed dynamic and Transmission-Gate Full Adder topologies, as opposite to the traditional approach based on cascaded Full Adders based on the same logic style. Analysis shows that the insertion of Transmission-Gate Full Adders between dynamic Full Adders does not violate the timing constraints that are required by the latter ones to achieve a correct operation. To evaluate the achievable performance, the proposed approach is compared with traditional domino Full Adder chains. Post- layout simulations on a 90-nm CMOS technology show that the proposed approach outperform the domino speed performance by more than 30%, without degrading the energy efficiency and with no area penalty.
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Delay Variability Due to Supply Variations in Transmission-Gate Full Adders
2007 IEEE International Symposium on Circuits and Systems, 2007Co-Authors: Massimo Alioto, Gaetano PalumboAbstract:In this paper, the delay variability due to supply variations is investiGated for the Transmission-Gate (TG) Full Adder topology, which is well known for its very low power consumption. The delay sensitivity with respect to supply variations is first analytically modeled. The resulting model is very simple, independent of the adopted technology and useful for better understanding the delay variations due to the supply voltage fluctuations. The delay sensitivity with respect to supply variations is also compared with that of traditional CMOS Full Adders, that are frequently adopted as a reference logic style. The results are validated by means of Spectre simulations with a 90-nm and a 0.18-μm technology.
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ISCAS - Delay Variability Due to Supply Variations in Transmission-Gate Full Adders
2007 IEEE International Symposium on Circuits and Systems, 2007Co-Authors: Massimo Alioto, Gaetano PalumboAbstract:In this paper, the delay variability due to supply variations is investiGated for the Transmission-Gate (TG) full adder topology, which is well known for its very low power consumption. The delay sensitivity with respect to supply variations is first analytically modeled. The resulting model is very simple, independent of the adopted technology and useful for better understanding the delay variations due to the supply voltage fluctuations. The delay sensitivity with respect to supply variations is also compared with that of traditional CMOS full adders, that are frequently adopted as a reference logic style. The results are validated by means of Spectre simulations with a 90-nm and a 0.18-mum technology.
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Very high-speed carry computation based on mixed dynamic/Transmission-Gate Full Adders
2007 18th European Conference on Circuit Theory and Design, 2007Co-Authors: Massimo Alioto, Gaetano PalumboAbstract:In this paper, a circuit design approach to perform very fast carry computation in cascaded Full Adders is proposed. The strategy is based on the adoption of mixed dynamic and Transmission-Gate Full Adder topologies, as opposite to the traditional approach based on cascaded Full Adders based on the same logic style. Analysis shows that the insertion of Transmission-Gate Full Adders between dynamic Full Adders does not violate the timing constraints that are required by the latter ones to achieve a correct operation. To evaluate the achievable performance, the proposed approach is compared with traditional domino Full Adder chains. Post- layout simulations on a 90-nm CMOS technology show that the proposed approach outperform the domino speed performance by more than 30%, without degrading the energy efficiency and with no area penalty.
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Very fast carry energy efficient computation based on mixed dynamic=Transmission-Gate full adders
Electronics Letters, 2007Co-Authors: Massimo Alioto, Gaetano PalumboAbstract:A circuit approach based on the adoption of mixed dynamic and Transmission-Gate full adder topologies to achieve very fast computation in carry chains is discussed. From a design point of view, the approach is very simple and allows the design to exceed the speed performance of fast Domino logic by more than 30% without degrading the energy efficiency. Post-layout simulations on a 90%nm CMOS technology are presented to validate the results.
Jun Yang - One of the best experts on this subject based on the ideXlab platform.
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TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS
IEEE Journal of Solid-state Circuits, 2020Co-Authors: Weiwei Shan, Chuan Zhang, Jun YangAbstract:Resilient circuits with timing error detection and correction (EDAC) can eliminate the excess timing margin but suffer from the short-path (SP) issue where SPs must be padded to exceed the detection window. SP padding (SPP) is similar to, but severer than, hold time fixing. Thus, it incurs significant area overhead, especially when working in the near-threshold region. In this article, we propose a Transmission Gate-based SPP (TG-SPP) method, which uses only one Transmission Gate to extend an SP to the negative clock phase while keeping the critical paths unaffected. Compared with the two-phase latch way or the conventional padding with tens to hundreds of buffers in an SP, our method efficiently decreases the overhead. We develop Transmission Gate insertion rules and an automatic insertion flow to overcome the complicated intersection problem of short and critical paths. To further reduce the EDAC area overhead, we also propose a lightweight error detection latch that has only two extra transistors compared to a conventional 24-T flip-flop for the conventional way. We implement all the proposed techniques in an SHA-256 chip using the 28-nm CMOS process. Results show that our TG-SPP method achieves the same padding effect as the two-phase latch-based method while reducing both the glitch power and sequential area overhead by a factor of 6 $\times $ . The fabricated resilient chips are measured to achieve 55%–405% frequency improvement and 38.6%–69.4% power saving compared with the typical margined baseline at the near-threshold region.
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TG-SPP: A One-Transmission-Gate Short-Path Padding for Wide-Voltage-Range Resilient Circuits in 28-nm CMOS
IEEE Journal of Solid-State Circuits, 2020Co-Authors: Weiwei Shan, Chuan Zhang, Jun YangAbstract:Resilient circuits with timing error detection and correction (EDAC) can eliminate the excess timing margin but suffer from the short-path (SP) issue where SPs must be padded to exceed the detection window. SP padding (SPP) is similar to, but severer than, hold time fixing. Thus, it incurs significant area overhead, especially when working in the near-threshold region. In this article, we propose a Transmission Gate-based SPP (TG-SPP) method, which uses only one Transmission Gate to extend an SP to the negative clock phase while keeping the critical paths unaffected. Compared with the two-phase latch way or the conventional padding with tens to hundreds of buffers in an SP, our method efficiently decreases the overhead. We develop Transmission Gate insertion rules and an automatic insertion flow to overcome the complicated intersection problem of short and critical paths. To further reduce the EDAC area overhead, we also propose a lightweight error detection latch that has only two extra transistors compared to a conventional 24-T flip-flop for the conventional way. We implement all the proposed techniques in an SHA-256 chip using the 28-nm CMOS process. Results show that our TG-SPP method achieves the same padding effect as the two-phase latch-based method while reducing both the glitch power and sequential area overhead by a factor of 6×. The fabricated resilient chips are measured to achieve 55%-405% frequency improvement and 38.6%-69.4% power saving compared with the typical margined baseline at the near-threshold region.
Bah-hwee Gwee - One of the best experts on this subject based on the ideXlab platform.
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Area-efficient and low stand-by power 1k-byte Transmission-Gate-based non-imprinting high-speed erase (TNIHE) SRAM
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016Co-Authors: Weng-geng Ho, Kyaw Zwa Lwin Ne, Prashanth N. Srinivas, Kwen-siong Chong, Bah-hwee GweeAbstract:We propose a novel 15-T Transmission-Gate-based Non-Imprinting High-speed Erase (TNIHE) SRAM cell with emphases on low area overhead and low stand-by power attributes for highly secured data storage applications. We benchmark our proposed 15-T TNIHE SRAM cell against the reported 22-T Non-Imprinting High-speed Erase (NIHE) SRAM cell, and demonstrated three key features of reducing 7 transistors. First, we adopt the Transmission Gates (as opposed the cross-couple inverters) in the slave circuitry, saving 4 transistors. Second, we eliminate a transistor which uses to reset the slave circuitry, hence saving 1 transistor. Third, we apply the global inverse transistors (as opposed to the local inverse transistors) in the read /write circuit for each SRAM cell, hence further reduce 2 more transistors. As a result, our proposed TNIHE SRAM cell @ 65nm CMOS features ~17% smaller layout area. We design a 1k-byte memory based on the proposed TNIHE SRAM cells. On the basis of simulations, we show that our 1k-byte SRAM memory features overall ~13% smaller area, and dissipates on average, ~30% lower stand-by power than the reported NIHE counterpart.
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ISCAS - Area-efficient and low stand-by power 1k-byte Transmission-Gate-based non-imprinting high-speed erase (TNIHE) SRAM
2016 IEEE International Symposium on Circuits and Systems (ISCAS), 2016Co-Authors: Weng-geng Ho, Kyaw Zwa Lwin Ne, Kwen-siong Chong, N. Prashanth Srinivas, Bah-hwee GweeAbstract:We propose a novel 15-T Transmission-Gate-based Non-Imprinting High-speed Erase (TNIHE) SRAM cell with emphases on low area overhead and low stand-by power attributes for highly secured data storage applications. We benchmark our proposed 15-T TNIHE SRAM cell against the reported 22-T Non-Imprinting High-speed Erase (NIHE) SRAM cell, and demonstrated three key features of reducing 7 transistors. First, we adopt the Transmission Gates (as opposed the cross-couple inverters) in the slave circuitry, saving 4 transistors. Second, we eliminate a transistor which uses to reset the slave circuitry, hence saving 1 transistor. Third, we apply the global inverse transistors (as opposed to the local inverse transistors) in the read /write circuit for each SRAM cell, hence further reduce 2 more transistors. As a result, our proposed TNIHE SRAM cell @ 65nm CMOS features ∼17% smaller layout area. We design a 1k-byte memory based on the proposed TNIHE SRAM cells. On the basis of simulations, we show that our 1k-byte SRAM memory features overall ∼13% smaller area, and dissipates on average, ∼30% lower stand-by power than the reported NIHE counterpart.
Anand Bulusu - One of the best experts on this subject based on the ideXlab platform.
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effective current model for inverter Transmission Gate structure and its application in circuit design
IEEE Transactions on Electron Devices, 2017Co-Authors: Arvind Sharma, Naushad Alam, Anand BulusuAbstract:In this paper, we present an effective switching current model ( ${I}_{\textsf {eff}}$ ) for inverter followed by a Transmission Gate structure (Inv-Tx) based on its switching trajectory. Unlike an inverter or NAND/NOR Gates, where ${I}_{\textsf {eff}}$ depends only on nMOSFET (pMOSFET) current for a falling (rising) transition, it is a function of both nMOSFET and pMOSFET currents for an Inv-Tx cell. The proposed model is verified against HSPICE simulations for a wide range of supply voltages and fan-outs at different technology nodes (e.g., 180, 130, and 65 nm). The model predicts the transition delay values with an average (maximum) error of 7% (11%) compared with HSPICE simulations. Synopsys TCAD Sentaurus simulations at 32-nm technology node are also used to validate the basic model assumptions. To demonstrate the utility of our model, design of some representative circuits while incorporating layout-dependent effects and inverse-narrow-width effect is presented. Finally, we show that a 256X1 multiplexer and a static D-flip-flop, with their transistor sizes and layout, optimized using the proposed model improves the performance of these circuits significantly over the conventional design methodologies.
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Effective Current Model for Inverter-Transmission Gate Structure and Its Application in Circuit Design
IEEE Transactions on Electron Devices, 2017Co-Authors: Arvind Sharma, Naushad Alam, Anand BulusuAbstract:In this paper, we present an effective switching current model (Ieff) for inverter followed by a Transmission Gate structure (Inv-Tx) based on its switching trajectory. Unlike an inverter or NAND/NOR Gates, where Ieff depends only on nMOSFET (pMOSFET) current for a falling (rising) transition, it is a function of both nMOSFET and pMOSFET currents for an Inv-Tx cell. The proposed model is verified against HSPICE simulations for a wide range of supply voltages and fan-outs at different technology nodes (e.g., 180, 130, and 65 nm). The model predicts the transition delay values with an average (maximum) error of 7% (11%) compared with HSPICE simulations. Synopsys TCAD Sentaurus simulations at 32-nm technology node are also used to validate the basic model assumptions. To demonstrate the utility of our model, design of some representative circuits while incorporating layout-dependent effects and inverse-narrow-width effect is presented. Finally, we show that a 256X1 multiplexer and a static D-flip-flop, with their transistor sizes and layout, optimized using the proposed model improves the performance of these circuits significantly over the conventional design methodologies.
