The Experts below are selected from a list of 177 Experts worldwide ranked by ideXlab platform
Randall L. Geiger - One of the best experts on this subject based on the ideXlab platform.
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analyses of static and dynamic random offset voltages in dynamic comparators
IEEE Transactions on Circuits and Systems, 2009Co-Authors: Jun He, Sanyi Zhan, Degang Chen, Randall L. GeigerAbstract:When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. In this paper, a novel balanced method is proposed to facilitate the evaluation of operating points of transistors in a dynamic comparator. Thus, it becomes possible to obtain an explicit expression for offset voltage in dynamic comparators. We include two types of mismatches in the Model: 1) static offset voltages from the mismatch in muCox and threshold voltage Vth and 2) dynamic offset voltage due to the mismatch in the parasitic capacitances. From the analytical Models, designers can obtain an intuition about the main contributors to offset and also fully explore the tradeoffs in dynamic comparator design, such as offset voltage, area and speed. To validate the balanced method, two topologies of dynamic comparator implemented in 0.25-mum and 40-nm CMOS technology are applied as examples. Input-referred offset voltages are first derived analytically based on SPICE Level 1 Model, whose values are compared with more accurate Monte Carlo transient simulations using a sophisticated BSIM3 Model. A good agreement between those two verifies the effectiveness of the balanced method. To illustrate its potential, the explicit expressions of offset voltage were applied to guide the optimization of ldquoLewis-Grayrdquo structure. Compared to the original design, the input offset voltage was easily reduced by 41% after the optimization while maintaining the same silicon area.
-
Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators
IEEE Transactions on Circuits and Systems I: Regular Papers, 2009Co-Authors: Sanyi Zhan, Degang Chen, Randall L. GeigerAbstract:When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. In this paper, a novel balanced method is proposed to facilitate the evaluation of operating points of transistors in a dynamic comparator. Thus, it becomes possible to obtain an explicit expression for offset voltage in dynamic comparators. We include two types of mismatches in the Model: 1) static offset voltages from the mismatch in muCox and threshold voltage Vth and 2) dynamic offset voltage due to the mismatch in the parasitic capacitances. From the analytical Models, designers can obtain an intuition about the main contributors to offset and also fully explore the tradeoffs in dynamic comparator design, such as offset voltage, area and speed. To validate the balanced method, two topologies of dynamic comparator implemented in 0.25-mum and 40-nm CMOS technology are applied as examples. Input-referred offset voltages are first derived analytically based on SPICE Level 1 Model, whose values are compared with more accurate Monte Carlo transient simulations using a sophisticated BSIM3 Model. A good agreement between those two verifies the effectiveness of the balanced method. To illustrate its potential, the explicit expressions of offset voltage were applied to guide the optimization of ldquoLewis-Grayrdquo structure. Compared to the original design, the input offset voltage was easily reduced by 41% after the optimization while maintaining the same silicon area.
-
ISCAS - A simple and accurate method to predict offset voltage in dynamic comparators
2008 IEEE International Symposium on Circuits and Systems, 2008Co-Authors: Jun He, Sanyi Zhan, Degang Chen, Randall L. GeigerAbstract:In a dynamic comparator, it's always challenging to analytically predict the input offset voltage due to the existence of the internal positive feedback and transient process. In this paper, a simple method is presented to accurately estimate input offset voltages caused by process variations in dynamic comparators. The "Lewis-Gray" comparator implemented in TSMC0.25mum process is applied as an example to verify the effectiveness of the analytical method. Based on the SPICE Level 1 Model, the method shows good agreements with Monte Carlo transient simulation based on the sophisticated BSEVI3V3 Model. The analytical results allow the circuit designers to fully explore the tradeoffs in comparator design, such as offset voltage, area and speed. To illustrate the potential, the analytical method was used to re-size the "Lewis-Gray" structure to reduce its random offset while maintaining a constant total area. After the optimization, input offset voltage has been reduced by 41% compared with its original sizing.
Sanyi Zhan - One of the best experts on this subject based on the ideXlab platform.
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analyses of static and dynamic random offset voltages in dynamic comparators
IEEE Transactions on Circuits and Systems, 2009Co-Authors: Jun He, Sanyi Zhan, Degang Chen, Randall L. GeigerAbstract:When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. In this paper, a novel balanced method is proposed to facilitate the evaluation of operating points of transistors in a dynamic comparator. Thus, it becomes possible to obtain an explicit expression for offset voltage in dynamic comparators. We include two types of mismatches in the Model: 1) static offset voltages from the mismatch in muCox and threshold voltage Vth and 2) dynamic offset voltage due to the mismatch in the parasitic capacitances. From the analytical Models, designers can obtain an intuition about the main contributors to offset and also fully explore the tradeoffs in dynamic comparator design, such as offset voltage, area and speed. To validate the balanced method, two topologies of dynamic comparator implemented in 0.25-mum and 40-nm CMOS technology are applied as examples. Input-referred offset voltages are first derived analytically based on SPICE Level 1 Model, whose values are compared with more accurate Monte Carlo transient simulations using a sophisticated BSIM3 Model. A good agreement between those two verifies the effectiveness of the balanced method. To illustrate its potential, the explicit expressions of offset voltage were applied to guide the optimization of ldquoLewis-Grayrdquo structure. Compared to the original design, the input offset voltage was easily reduced by 41% after the optimization while maintaining the same silicon area.
-
Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators
IEEE Transactions on Circuits and Systems I: Regular Papers, 2009Co-Authors: Sanyi Zhan, Degang Chen, Randall L. GeigerAbstract:When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. In this paper, a novel balanced method is proposed to facilitate the evaluation of operating points of transistors in a dynamic comparator. Thus, it becomes possible to obtain an explicit expression for offset voltage in dynamic comparators. We include two types of mismatches in the Model: 1) static offset voltages from the mismatch in muCox and threshold voltage Vth and 2) dynamic offset voltage due to the mismatch in the parasitic capacitances. From the analytical Models, designers can obtain an intuition about the main contributors to offset and also fully explore the tradeoffs in dynamic comparator design, such as offset voltage, area and speed. To validate the balanced method, two topologies of dynamic comparator implemented in 0.25-mum and 40-nm CMOS technology are applied as examples. Input-referred offset voltages are first derived analytically based on SPICE Level 1 Model, whose values are compared with more accurate Monte Carlo transient simulations using a sophisticated BSIM3 Model. A good agreement between those two verifies the effectiveness of the balanced method. To illustrate its potential, the explicit expressions of offset voltage were applied to guide the optimization of ldquoLewis-Grayrdquo structure. Compared to the original design, the input offset voltage was easily reduced by 41% after the optimization while maintaining the same silicon area.
-
ISCAS - A simple and accurate method to predict offset voltage in dynamic comparators
2008 IEEE International Symposium on Circuits and Systems, 2008Co-Authors: Jun He, Sanyi Zhan, Degang Chen, Randall L. GeigerAbstract:In a dynamic comparator, it's always challenging to analytically predict the input offset voltage due to the existence of the internal positive feedback and transient process. In this paper, a simple method is presented to accurately estimate input offset voltages caused by process variations in dynamic comparators. The "Lewis-Gray" comparator implemented in TSMC0.25mum process is applied as an example to verify the effectiveness of the analytical method. Based on the SPICE Level 1 Model, the method shows good agreements with Monte Carlo transient simulation based on the sophisticated BSEVI3V3 Model. The analytical results allow the circuit designers to fully explore the tradeoffs in comparator design, such as offset voltage, area and speed. To illustrate the potential, the analytical method was used to re-size the "Lewis-Gray" structure to reduce its random offset while maintaining a constant total area. After the optimization, input offset voltage has been reduced by 41% compared with its original sizing.
Jun He - One of the best experts on this subject based on the ideXlab platform.
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analyses of static and dynamic random offset voltages in dynamic comparators
IEEE Transactions on Circuits and Systems, 2009Co-Authors: Jun He, Sanyi Zhan, Degang Chen, Randall L. GeigerAbstract:When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. In this paper, a novel balanced method is proposed to facilitate the evaluation of operating points of transistors in a dynamic comparator. Thus, it becomes possible to obtain an explicit expression for offset voltage in dynamic comparators. We include two types of mismatches in the Model: 1) static offset voltages from the mismatch in muCox and threshold voltage Vth and 2) dynamic offset voltage due to the mismatch in the parasitic capacitances. From the analytical Models, designers can obtain an intuition about the main contributors to offset and also fully explore the tradeoffs in dynamic comparator design, such as offset voltage, area and speed. To validate the balanced method, two topologies of dynamic comparator implemented in 0.25-mum and 40-nm CMOS technology are applied as examples. Input-referred offset voltages are first derived analytically based on SPICE Level 1 Model, whose values are compared with more accurate Monte Carlo transient simulations using a sophisticated BSIM3 Model. A good agreement between those two verifies the effectiveness of the balanced method. To illustrate its potential, the explicit expressions of offset voltage were applied to guide the optimization of ldquoLewis-Grayrdquo structure. Compared to the original design, the input offset voltage was easily reduced by 41% after the optimization while maintaining the same silicon area.
-
ISCAS - A simple and accurate method to predict offset voltage in dynamic comparators
2008 IEEE International Symposium on Circuits and Systems, 2008Co-Authors: Jun He, Sanyi Zhan, Degang Chen, Randall L. GeigerAbstract:In a dynamic comparator, it's always challenging to analytically predict the input offset voltage due to the existence of the internal positive feedback and transient process. In this paper, a simple method is presented to accurately estimate input offset voltages caused by process variations in dynamic comparators. The "Lewis-Gray" comparator implemented in TSMC0.25mum process is applied as an example to verify the effectiveness of the analytical method. Based on the SPICE Level 1 Model, the method shows good agreements with Monte Carlo transient simulation based on the sophisticated BSEVI3V3 Model. The analytical results allow the circuit designers to fully explore the tradeoffs in comparator design, such as offset voltage, area and speed. To illustrate the potential, the analytical method was used to re-size the "Lewis-Gray" structure to reduce its random offset while maintaining a constant total area. After the optimization, input offset voltage has been reduced by 41% compared with its original sizing.
Degang Chen - One of the best experts on this subject based on the ideXlab platform.
-
analyses of static and dynamic random offset voltages in dynamic comparators
IEEE Transactions on Circuits and Systems, 2009Co-Authors: Jun He, Sanyi Zhan, Degang Chen, Randall L. GeigerAbstract:When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. In this paper, a novel balanced method is proposed to facilitate the evaluation of operating points of transistors in a dynamic comparator. Thus, it becomes possible to obtain an explicit expression for offset voltage in dynamic comparators. We include two types of mismatches in the Model: 1) static offset voltages from the mismatch in muCox and threshold voltage Vth and 2) dynamic offset voltage due to the mismatch in the parasitic capacitances. From the analytical Models, designers can obtain an intuition about the main contributors to offset and also fully explore the tradeoffs in dynamic comparator design, such as offset voltage, area and speed. To validate the balanced method, two topologies of dynamic comparator implemented in 0.25-mum and 40-nm CMOS technology are applied as examples. Input-referred offset voltages are first derived analytically based on SPICE Level 1 Model, whose values are compared with more accurate Monte Carlo transient simulations using a sophisticated BSIM3 Model. A good agreement between those two verifies the effectiveness of the balanced method. To illustrate its potential, the explicit expressions of offset voltage were applied to guide the optimization of ldquoLewis-Grayrdquo structure. Compared to the original design, the input offset voltage was easily reduced by 41% after the optimization while maintaining the same silicon area.
-
Analyses of Static and Dynamic Random Offset Voltages in Dynamic Comparators
IEEE Transactions on Circuits and Systems I: Regular Papers, 2009Co-Authors: Sanyi Zhan, Degang Chen, Randall L. GeigerAbstract:When mismatches are present in a dynamic comparator, due to internal positive feedback and transient response, it is always challenging to analytically predict the input-referred random offset voltages since the operating points of transistors are time varying. In this paper, a novel balanced method is proposed to facilitate the evaluation of operating points of transistors in a dynamic comparator. Thus, it becomes possible to obtain an explicit expression for offset voltage in dynamic comparators. We include two types of mismatches in the Model: 1) static offset voltages from the mismatch in muCox and threshold voltage Vth and 2) dynamic offset voltage due to the mismatch in the parasitic capacitances. From the analytical Models, designers can obtain an intuition about the main contributors to offset and also fully explore the tradeoffs in dynamic comparator design, such as offset voltage, area and speed. To validate the balanced method, two topologies of dynamic comparator implemented in 0.25-mum and 40-nm CMOS technology are applied as examples. Input-referred offset voltages are first derived analytically based on SPICE Level 1 Model, whose values are compared with more accurate Monte Carlo transient simulations using a sophisticated BSIM3 Model. A good agreement between those two verifies the effectiveness of the balanced method. To illustrate its potential, the explicit expressions of offset voltage were applied to guide the optimization of ldquoLewis-Grayrdquo structure. Compared to the original design, the input offset voltage was easily reduced by 41% after the optimization while maintaining the same silicon area.
-
ISCAS - A simple and accurate method to predict offset voltage in dynamic comparators
2008 IEEE International Symposium on Circuits and Systems, 2008Co-Authors: Jun He, Sanyi Zhan, Degang Chen, Randall L. GeigerAbstract:In a dynamic comparator, it's always challenging to analytically predict the input offset voltage due to the existence of the internal positive feedback and transient process. In this paper, a simple method is presented to accurately estimate input offset voltages caused by process variations in dynamic comparators. The "Lewis-Gray" comparator implemented in TSMC0.25mum process is applied as an example to verify the effectiveness of the analytical method. Based on the SPICE Level 1 Model, the method shows good agreements with Monte Carlo transient simulation based on the sophisticated BSEVI3V3 Model. The analytical results allow the circuit designers to fully explore the tradeoffs in comparator design, such as offset voltage, area and speed. To illustrate the potential, the analytical method was used to re-size the "Lewis-Gray" structure to reduce its random offset while maintaining a constant total area. After the optimization, input offset voltage has been reduced by 41% compared with its original sizing.
Philip G. Neudeck - One of the best experts on this subject based on the ideXlab platform.
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First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits
2016Co-Authors: Philip G. Neudeck, David J. Spry, Liang-yu ChenAbstract:Abstract A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two Levels of metal interconnect have reproducibly demonstrated electrical operation at 500 °C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided Modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 °C to 500 °C SPICE simulation Models of first-order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC Modeling is implemented using the baseline-version SPICE NMOS Level 1 Model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device Models is veri...
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First-Order SPICE Modeling of Extreme-Temperature 4H-SiC JFET Integrated Circuits
Additional Conferences (Device Packaging HiTEC HiTEN and CICMT), 2016Co-Authors: Philip G. Neudeck, David J. Spry, Liang-yu ChenAbstract:Abstract A separate submission to this conference reports that 4H-SiC Junction Field Effect Transistor (JFET) digital and analog Integrated Circuits (ICs) with two Levels of metal interconnect have reproducibly demonstrated electrical operation at 500 °C in excess of 1000 hours. While this progress expands the complexity and durability envelope of high temperature ICs, one important area for further technology maturation is the development of reasonably accurate and accessible computer-aided Modeling and simulation tools for circuit design of these ICs. Towards this end, we report on development and verification of 25 °C to 500 °C SPICE simulation Models of first-order accuracy for this extreme-temperature durable 4H-SiC JFET IC technology. For maximum availability, the JFET IC Modeling is implemented using the baseline-version SPICE NMOS Level 1 Model that is common to other variations of SPICE software and importantly includes the body-bias effect. The first-order accuracy of these device Models is verified by direct comparison with measured experimental device characteristics.
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SiC JFET Transistor Circuit Model for Extreme Temperature Range
2008Co-Authors: Philip G. NeudeckAbstract:A technique for simulating extreme-temperature operation of integrated circuits that incorporate silicon carbide (SiC) junction field-effect transistors (JFETs) has been developed. The technique involves modification of NGSPICE, which is an open-source version of the popular Simulation Program with Integrated Circuit Emphasis (SPICE) general-purpose analog-integrated-circuit-simulating software. NGSPICE in its unmodified form is used for simulating and designing circuits made from silicon-based transistors that operate at or near room temperature. Two rapid modifications of NGSPICE source code enable SiC JFETs to be simulated to 500 C using the well-known Level 1 Model for silicon metal oxide semiconductor field-effect transistors (MOSFETs). First, the default value of the MOSFET surface potential must be changed. In the unmodified source code, this parameter has a value of 0.6, which corresponds to slightly more than half the bandgap of silicon. In NGSPICE modified to simulate SiC JFETs, this parameter is changed to a value of 1.6, corresponding to slightly more than half the bandgap of SiC. The second modification consists of changing the temperature dependence of MOSFET transconductance and saturation parameters. The unmodified NGSPICE source code implements a T(sup -1.5) temperature dependence for these parameters. In order to mimic the temperature behavior of experimental SiC JFETs, a T(sup -1.3) temperature dependence must be implemented in the NGSPICE source code. Following these two simple modifications, the Level 1 MOSFET Model of the NGSPICE circuit simulation program reasonably approximates the measured high-temperature behavior of experimental SiC JFETs properly operated with zero or reverse bias applied to the gate terminal. Modification of additional silicon parameters in the NGSPICE source code was not necessary to Model experimental SiC JFET current-voltage performance across the entire temperature range from 25 to 500 C.