The Experts below are selected from a list of 187296 Experts worldwide ranked by ideXlab platform
Arnan Mitchell - One of the best experts on this subject based on the ideXlab platform.
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A novel Surface Tension Assisted Lithography (STAL) technique for microfabrication of 3D structures
J. Mater. Chem. C, 2013Co-Authors: Mahyar Nasabi, Francisco J. Tovar-lopez, Gorgi Kostovski, Khashayar Khoshmanesh, Arnan MitchellAbstract:A novel Surface Tension Assisted Lithography (STAL) technique is proposed to fabricate 3D structures in the photo-patternable polymer, SU-8, using a sequence of soft-imprint Lithography, photo-Lithography, and polymer reflow. The dimensions of the reflowed 3D structures are controlled by the volume of material initially displaced by soft-imprinting, and the lateral dimensions of the reflow container, defined by photo-Lithography. © The Royal Society of Chemistry 2013.
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a novel surface tension assisted Lithography stal technique for microfabrication of 3d structures
Journal of Materials Chemistry C, 2013Co-Authors: Mahyar Nasabi, Gorgi Kostovski, Khashayar Khoshmanesh, Francisco J Tovarlopez, Arnan MitchellAbstract:A novel Surface Tension Assisted Lithography (STAL) technique is proposed to fabricate 3D structures in the photo-patternable polymer, SU-8, using a sequence of soft-imprint Lithography, photo-Lithography, and polymer reflow. The dimensions of the reflowed 3D structures are controlled by the volume of material initially displaced by soft-imprinting, and the lateral dimensions of the reflow container, defined by photo-Lithography.
Chenming Hu - One of the best experts on this subject based on the ideXlab platform.
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Nanoscale CMOS spacer FinFET for the terabit era
IEEE Electron Device Letters, 2002Co-Authors: Yang-kyu Choi, Tsu-jae King, Chenming HuAbstract:A spacer Lithography process technology, which uses a sacrificial\nlayer and spacer layer formed by chemical vapor deposition (CVD), has\nbeen developed. It has been applied to make a sub-40-nm Si-fin structure\nfor a double-gate FinFET with conventional dry etching for the first\ntime. The minimum-sized features are defined not by the photoLithography\nbut by the CVD film thickness. Therefore, this spacer Lithography\ntechnology yields better critical dimension uniformity than conventional\noptical or e-beam Lithography and defines smaller features beyond the\nlimit of current Lithography technology. It also provides a doubling of\nfeature density for a given Lithography pitch, which increases current\nby a factor of two. To demonstrate this spacer Lithography technology,\nSi-fin structures have been patterned for planar double-gate CMOS FinFET\ndevices
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Spacer FinFET: Nano-scale CMOS technology for the terabit era
2001 International Semiconductor Device Research Symposium ISDRS 2001 - Proceedings, 2001Co-Authors: Yang-kyu Choi, Tsu-jae King, Chenming HuAbstract:A spacer Lithography technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-40 nm structures with conventional dry etching. The minimum-sized features are finished not by photoLithography but by the CVD film thickness. Therefore the spacer Lithography technology yields critical dimension variations of minimum-sized features which are much smaller than achieved by optical or e-beam Lithography. It also provides a doubling of device density for a given Lithography pitch. This spacer Lithography technology is used to pattern silicon-fin structures for double-gate MOSFETs and CMOS FinFET results are reported. © 2002 Elsevier Science Ltd. All rights reserved.
David N. Reinhoudt - One of the best experts on this subject based on the ideXlab platform.
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Stamps for Submicrometer Soft Lithography Fabricated by Capillary Force Lithography
Advanced Materials, 2004Co-Authors: Christiaan M Bruinink, Laurens Kuipers, Mária Péter, Jurriaan Huskens, De M.j. Boer, David N. ReinhoudtAbstract:Lithography, capillary force • Lithography, soft • Replica molding • Stamps
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Stamps for submicrometer soft Lithography fabricated by capillary force Lithography
Advanced Materials, 2004Co-Authors: Christiaan M Bruinink, Meint De Boer, Laurens Kuipers, Mária Péter, Jurriaan Huskens, David N. ReinhoudtAbstract:PhotoLithography has been the main technology for integrated circuit (IC) fabrication during the last few decades,([1]) however its extension to the sub-100 nm range requires the development of advanced lithographic techniques, e.g., deep UV and extreme UV photoLithography,([2,3]) soft X-ray Lithography,([4]) electron-beam writing,([5]) and ion-beam Lithography.([6]) However, the costs render these techniques less suitable for exploratory research applications, in which requirements such as pattern uniformity, reproducibility, and accurate alignment are not stringent. Complementary non-photolithographic techniques, including soft Lithography,([7]) nanoimprint Lithography (NIL),([8]) and capillary force Lithography (CFL)([9]) have been developed successfully during the last decade in the field of micro- and nanofabrication.
Mahyar Nasabi - One of the best experts on this subject based on the ideXlab platform.
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A novel Surface Tension Assisted Lithography (STAL) technique for microfabrication of 3D structures
J. Mater. Chem. C, 2013Co-Authors: Mahyar Nasabi, Francisco J. Tovar-lopez, Gorgi Kostovski, Khashayar Khoshmanesh, Arnan MitchellAbstract:A novel Surface Tension Assisted Lithography (STAL) technique is proposed to fabricate 3D structures in the photo-patternable polymer, SU-8, using a sequence of soft-imprint Lithography, photo-Lithography, and polymer reflow. The dimensions of the reflowed 3D structures are controlled by the volume of material initially displaced by soft-imprinting, and the lateral dimensions of the reflow container, defined by photo-Lithography. © The Royal Society of Chemistry 2013.
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a novel surface tension assisted Lithography stal technique for microfabrication of 3d structures
Journal of Materials Chemistry C, 2013Co-Authors: Mahyar Nasabi, Gorgi Kostovski, Khashayar Khoshmanesh, Francisco J Tovarlopez, Arnan MitchellAbstract:A novel Surface Tension Assisted Lithography (STAL) technique is proposed to fabricate 3D structures in the photo-patternable polymer, SU-8, using a sequence of soft-imprint Lithography, photo-Lithography, and polymer reflow. The dimensions of the reflowed 3D structures are controlled by the volume of material initially displaced by soft-imprinting, and the lateral dimensions of the reflow container, defined by photo-Lithography.
Yang-kyu Choi - One of the best experts on this subject based on the ideXlab platform.
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Nanoscale CMOS spacer FinFET for the terabit era
IEEE Electron Device Letters, 2002Co-Authors: Yang-kyu Choi, Tsu-jae King, Chenming HuAbstract:A spacer Lithography process technology, which uses a sacrificial\nlayer and spacer layer formed by chemical vapor deposition (CVD), has\nbeen developed. It has been applied to make a sub-40-nm Si-fin structure\nfor a double-gate FinFET with conventional dry etching for the first\ntime. The minimum-sized features are defined not by the photoLithography\nbut by the CVD film thickness. Therefore, this spacer Lithography\ntechnology yields better critical dimension uniformity than conventional\noptical or e-beam Lithography and defines smaller features beyond the\nlimit of current Lithography technology. It also provides a doubling of\nfeature density for a given Lithography pitch, which increases current\nby a factor of two. To demonstrate this spacer Lithography technology,\nSi-fin structures have been patterned for planar double-gate CMOS FinFET\ndevices
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Spacer FinFET: Nano-scale CMOS technology for the terabit era
2001 International Semiconductor Device Research Symposium ISDRS 2001 - Proceedings, 2001Co-Authors: Yang-kyu Choi, Tsu-jae King, Chenming HuAbstract:A spacer Lithography technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-40 nm structures with conventional dry etching. The minimum-sized features are finished not by photoLithography but by the CVD film thickness. Therefore the spacer Lithography technology yields critical dimension variations of minimum-sized features which are much smaller than achieved by optical or e-beam Lithography. It also provides a doubling of device density for a given Lithography pitch. This spacer Lithography technology is used to pattern silicon-fin structures for double-gate MOSFETs and CMOS FinFET results are reported. © 2002 Elsevier Science Ltd. All rights reserved.
