The Experts below are selected from a list of 81 Experts worldwide ranked by ideXlab platform

Rajiv Gupta - One of the best experts on this subject based on the ideXlab platform.

  • MICRO - Executing loops on a fine-grained MIMD Architecture
    Proceedings of the 24th annual international symposium on Microarchitecture - MICRO 24, 1991
    Co-Authors: Rajiv Gupta
    Abstract:

    We present techniques for exploiting parallelism extracted from loops on an MIMD system. Parallelism is exploited through parallel execution of instructions on multiple processors as well as pipelined nature of individual processors. The processors based upon the load/store Architecture read/write operands frotn/to private registers, shared registers, and channel queues. If the communication of a vahte from one processor to another requires synchronization then a channel is used otherwise a shared register is used to communicate the vahte. The reeeiving processor reads the values from a channel queue in the order they are written to the channel by the sending processor. The scheduling of operations is carried out in a manner that reduces interprocessor communication. Such schedules reduce the likelihood of one processor impeding the progress of other processors.

  • MICRO - A fine-grained MIMD Architecture based upon register channels
    [1990] Proceedings of the 23rd Annual Workshop and Symposium@m_MICRO 23: Microprogramming and Microarchitecture, 1990
    Co-Authors: Rajiv Gupta
    Abstract:

    This paper discusses the use of shared register channels as a data exchange mechanism among processors in a fine-grained MIMD system with a load/store Architecture. A register channel is provided with a synchronization bit that is used to ensure that a processor succeeds in reading a channel only after a value has been written to the channel. The instructions supported by this load/store Architecture allow both registers and register channels to be used as operand sources and result destinations. Conditional load, store, and move instructions are provided to allow processors to exchange values through channels in presence of aliasing caused by array references. Compiler support required to take proper advantage of channels is briefly discussed. In contrast to a VLIW machine a system with channels does not require strict lockstep operation of its processors. This reduces the delays caused by unpredictable events such as memory bank conflicts. >

O. Danieli - One of the best experts on this subject based on the ideXlab platform.

  • ISCA - Performance comparison of load/store and symmetric instruction set Architectures
    Proceedings of the 17th annual international symposium on Computer Architecture - ISCA '90, 1990
    Co-Authors: D. Alpert, Amir Averbuch, O. Danieli
    Abstract:

    Is it true that a Load/Store Architecture is both simpler and faster than a Symmetric Architecture, or does the Symmetric Architecture offer a potential performance advantage that can be realized by the use of additional hardware? In order to answer it quantitatively, we simulated two models that were equal in all aspects except the factor that we measure. We found that the Load/Store model executes 12% more instructions but only 4% more cycles.

Vojin G. Oklobdzija - One of the best experts on this subject based on the ideXlab platform.

  • Wiley Encyclopedia of Computer Science and Engineering - Reduced Instruction Set Computing
    Wiley Encyclopedia of Computer Science and Engineering, 2009
    Co-Authors: Vojin G. Oklobdzija
    Abstract:

    Reduced instruction set computing (RISC) Architecture started as a fresh look at existing ideas. The main featue of RISC is the architectural support for the exploitation of parallelism on the instruction level. All distinguished features of RISC should be considered in light of their support for the RISC pipeline. Keywords: IBM 801; RISC; computer Architecture; load/store Architecture; instruction sets; pipelining; superscalar machines; superpipeline machines; optimizing compiler; branch and execute; delayed branch; cache; Harvard Architecture; delayed load; superscalar; superpipelined

  • Reduced Instruction Set Computing
    Wiley Encyclopedia of Electrical and Electronics Engineering, 1999
    Co-Authors: Vojin G. Oklobdzija
    Abstract:

    The sections in this article are 1 Architecture 2 Risc Machine Implementation 3 Historical Perspective Keywords: IBM 801; RISC; computer Architecture; load/store Architecture; instruction sets; pipelining; superscalar machines; superpipeline machines; optimizing compiler; branch and execute; delayed branch; cache; harvard Architecture; delayed load; superscalar; superpipelined

D. Alpert - One of the best experts on this subject based on the ideXlab platform.

  • ISCA - Performance comparison of load/store and symmetric instruction set Architectures
    Proceedings of the 17th annual international symposium on Computer Architecture - ISCA '90, 1990
    Co-Authors: D. Alpert, Amir Averbuch, O. Danieli
    Abstract:

    Is it true that a Load/Store Architecture is both simpler and faster than a Symmetric Architecture, or does the Symmetric Architecture offer a potential performance advantage that can be realized by the use of additional hardware? In order to answer it quantitatively, we simulated two models that were equal in all aspects except the factor that we measure. We found that the Load/Store model executes 12% more instructions but only 4% more cycles.

Detlef Jantz - One of the best experts on this subject based on the ideXlab platform.

  • The Perm Architecture approach: Supporting embedded system development
    IFAC Proceedings Volumes, 2006
    Co-Authors: Christian Siemers, Detlef Jantz
    Abstract:

    Abstract Despite of innovations in computer science software technology as high level languages, object-oriented programming, memory management units and operating systems with some security functions, software is still afflicted with the fault of a certain unreliability. Coarse-grained segment or page protection mechanism in hardware works with fix-sized memory blocks. A sufficient technique for a fine-grained protection mechanism down to a byte size resolution is still missing. This work has led to the new PERM (Protection Enhanced RISC Machine) processor Architecture introducing a new approach to this problem. The Load-Store Architecture of a RISC machine leads to a consistent realization of an enhanced address pointer procedure. This is combined with the ability to use much more information about the data objects and implements an effective data protection of all data in the processor's address range. This paper shows the effectiveness of the processor enhancement and gives some hints for its use inside embedded system development.