The Experts below are selected from a list of 10506 Experts worldwide ranked by ideXlab platform
Borivoje Nikolic - One of the best experts on this subject based on the ideXlab platform.
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a real time 1 89 ghz bandwidth 175 khz resolution sparse spectral analysis risc v soc in 16 nm finfet
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Angie Wang, Woorham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje NikolicAbstract:A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis system-on-chip (SoC), integrating a subsampling analog-to-digital converter (ADC) frontend with a digital reconstruction backend and implementing a 21 600-point sparse Fourier transform based on the fast Fourier aliasing-based sparse transform (FFAST) algorithm has been co-designed by using the Constructing Hardware in a Scala Embedded Language (Chisel) and Berkeley Analog Generator (BAG) circuit generator frameworks in 16-nm CMOS. Three sets of $25\times $ , $27\times $ , and $32\times $ subsampling successive approximation register (SAR) ADCs acquire signal with ~5.4–6.3 effective number of bits (ENOB)/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point fast Fourier transforms (FFTs), a signal Location Estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order, fifth-generation reduced instruction set (RISC-V) Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8 mW with a 3.78-GHz reference clock. At 400 MHz and 0.7-V digital supply voltage (VDD), the Rocket core and the FFAST digital signal processing (DSP) together consume 133.5 mW.
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a real time analog digital co designed 1 89 ghz bandwidth 175 khz resolution sparse spectral analysis risc v soc in 16 nm finfet
European Solid-State Circuits Conference, 2018Co-Authors: Angie Wang, Woorham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje NikolicAbstract:A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis SoC, integrating a subsampling ADC frontend with a digital reconstruction backend and implementing a 21,600-point FFAST sparse FFT [1] has been generated using the Chisel [2] and BAG [3] frameworks in 16-nm CMOS. Three sets of 25×, 27×, and 32×subsampling SAR ADCs acquire signal with ~5.4-6.3 ENOB/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point FFTs, a signal Location Estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order RISC-V Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8mW with a 3.78-GHz input clock. At 400MHz and 0.7-V VDD, the Rocket core and the FFAST DSP together consume 133.5mW.
Angie Wang - One of the best experts on this subject based on the ideXlab platform.
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a real time 1 89 ghz bandwidth 175 khz resolution sparse spectral analysis risc v soc in 16 nm finfet
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Angie Wang, Woorham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje NikolicAbstract:A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis system-on-chip (SoC), integrating a subsampling analog-to-digital converter (ADC) frontend with a digital reconstruction backend and implementing a 21 600-point sparse Fourier transform based on the fast Fourier aliasing-based sparse transform (FFAST) algorithm has been co-designed by using the Constructing Hardware in a Scala Embedded Language (Chisel) and Berkeley Analog Generator (BAG) circuit generator frameworks in 16-nm CMOS. Three sets of $25\times $ , $27\times $ , and $32\times $ subsampling successive approximation register (SAR) ADCs acquire signal with ~5.4–6.3 effective number of bits (ENOB)/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point fast Fourier transforms (FFTs), a signal Location Estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order, fifth-generation reduced instruction set (RISC-V) Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8 mW with a 3.78-GHz reference clock. At 400 MHz and 0.7-V digital supply voltage (VDD), the Rocket core and the FFAST digital signal processing (DSP) together consume 133.5 mW.
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a real time analog digital co designed 1 89 ghz bandwidth 175 khz resolution sparse spectral analysis risc v soc in 16 nm finfet
European Solid-State Circuits Conference, 2018Co-Authors: Angie Wang, Woorham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje NikolicAbstract:A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis SoC, integrating a subsampling ADC frontend with a digital reconstruction backend and implementing a 21,600-point FFAST sparse FFT [1] has been generated using the Chisel [2] and BAG [3] frameworks in 16-nm CMOS. Three sets of 25×, 27×, and 32×subsampling SAR ADCs acquire signal with ~5.4-6.3 ENOB/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point FFTs, a signal Location Estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order RISC-V Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8mW with a 3.78-GHz input clock. At 400MHz and 0.7-V VDD, the Rocket core and the FFAST DSP together consume 133.5mW.
Orhan Ocal - One of the best experts on this subject based on the ideXlab platform.
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a real time 1 89 ghz bandwidth 175 khz resolution sparse spectral analysis risc v soc in 16 nm finfet
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Angie Wang, Woorham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje NikolicAbstract:A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis system-on-chip (SoC), integrating a subsampling analog-to-digital converter (ADC) frontend with a digital reconstruction backend and implementing a 21 600-point sparse Fourier transform based on the fast Fourier aliasing-based sparse transform (FFAST) algorithm has been co-designed by using the Constructing Hardware in a Scala Embedded Language (Chisel) and Berkeley Analog Generator (BAG) circuit generator frameworks in 16-nm CMOS. Three sets of $25\times $ , $27\times $ , and $32\times $ subsampling successive approximation register (SAR) ADCs acquire signal with ~5.4–6.3 effective number of bits (ENOB)/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point fast Fourier transforms (FFTs), a signal Location Estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order, fifth-generation reduced instruction set (RISC-V) Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8 mW with a 3.78-GHz reference clock. At 400 MHz and 0.7-V digital supply voltage (VDD), the Rocket core and the FFAST digital signal processing (DSP) together consume 133.5 mW.
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a real time analog digital co designed 1 89 ghz bandwidth 175 khz resolution sparse spectral analysis risc v soc in 16 nm finfet
European Solid-State Circuits Conference, 2018Co-Authors: Angie Wang, Woorham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje NikolicAbstract:A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis SoC, integrating a subsampling ADC frontend with a digital reconstruction backend and implementing a 21,600-point FFAST sparse FFT [1] has been generated using the Chisel [2] and BAG [3] frameworks in 16-nm CMOS. Three sets of 25×, 27×, and 32×subsampling SAR ADCs acquire signal with ~5.4-6.3 ENOB/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point FFTs, a signal Location Estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order RISC-V Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8mW with a 3.78-GHz input clock. At 400MHz and 0.7-V VDD, the Rocket core and the FFAST DSP together consume 133.5mW.
Woorham Bae - One of the best experts on this subject based on the ideXlab platform.
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a real time 1 89 ghz bandwidth 175 khz resolution sparse spectral analysis risc v soc in 16 nm finfet
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Angie Wang, Woorham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje NikolicAbstract:A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis system-on-chip (SoC), integrating a subsampling analog-to-digital converter (ADC) frontend with a digital reconstruction backend and implementing a 21 600-point sparse Fourier transform based on the fast Fourier aliasing-based sparse transform (FFAST) algorithm has been co-designed by using the Constructing Hardware in a Scala Embedded Language (Chisel) and Berkeley Analog Generator (BAG) circuit generator frameworks in 16-nm CMOS. Three sets of $25\times $ , $27\times $ , and $32\times $ subsampling successive approximation register (SAR) ADCs acquire signal with ~5.4–6.3 effective number of bits (ENOB)/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point fast Fourier transforms (FFTs), a signal Location Estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order, fifth-generation reduced instruction set (RISC-V) Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8 mW with a 3.78-GHz reference clock. At 400 MHz and 0.7-V digital supply voltage (VDD), the Rocket core and the FFAST digital signal processing (DSP) together consume 133.5 mW.
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a real time analog digital co designed 1 89 ghz bandwidth 175 khz resolution sparse spectral analysis risc v soc in 16 nm finfet
European Solid-State Circuits Conference, 2018Co-Authors: Angie Wang, Woorham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje NikolicAbstract:A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis SoC, integrating a subsampling ADC frontend with a digital reconstruction backend and implementing a 21,600-point FFAST sparse FFT [1] has been generated using the Chisel [2] and BAG [3] frameworks in 16-nm CMOS. Three sets of 25×, 27×, and 32×subsampling SAR ADCs acquire signal with ~5.4-6.3 ENOB/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point FFTs, a signal Location Estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order RISC-V Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8mW with a 3.78-GHz input clock. At 400MHz and 0.7-V VDD, the Rocket core and the FFAST DSP together consume 133.5mW.
Jaeduk Han - One of the best experts on this subject based on the ideXlab platform.
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a real time 1 89 ghz bandwidth 175 khz resolution sparse spectral analysis risc v soc in 16 nm finfet
IEEE Journal of Solid-state Circuits, 2019Co-Authors: Angie Wang, Woorham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje NikolicAbstract:A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis system-on-chip (SoC), integrating a subsampling analog-to-digital converter (ADC) frontend with a digital reconstruction backend and implementing a 21 600-point sparse Fourier transform based on the fast Fourier aliasing-based sparse transform (FFAST) algorithm has been co-designed by using the Constructing Hardware in a Scala Embedded Language (Chisel) and Berkeley Analog Generator (BAG) circuit generator frameworks in 16-nm CMOS. Three sets of $25\times $ , $27\times $ , and $32\times $ subsampling successive approximation register (SAR) ADCs acquire signal with ~5.4–6.3 effective number of bits (ENOB)/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point fast Fourier transforms (FFTs), a signal Location Estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order, fifth-generation reduced instruction set (RISC-V) Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8 mW with a 3.78-GHz reference clock. At 400 MHz and 0.7-V digital supply voltage (VDD), the Rocket core and the FFAST digital signal processing (DSP) together consume 133.5 mW.
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a real time analog digital co designed 1 89 ghz bandwidth 175 khz resolution sparse spectral analysis risc v soc in 16 nm finfet
European Solid-State Circuits Conference, 2018Co-Authors: Angie Wang, Woorham Bae, Jaeduk Han, Stevo Bailey, Paul Rigge, Orhan Ocal, Zhongkai Wang, Kannan Ramchandran, Elad Alon, Borivoje NikolicAbstract:A 1.89-GHz bandwidth, 175-kHz resolution spectral analysis SoC, integrating a subsampling ADC frontend with a digital reconstruction backend and implementing a 21,600-point FFAST sparse FFT [1] has been generated using the Chisel [2] and BAG [3] frameworks in 16-nm CMOS. Three sets of 25×, 27×, and 32×subsampling SAR ADCs acquire signal with ~5.4-6.3 ENOB/slice. The digital backend consists of mixed-radix 864-, 800-, and 675-point FFTs, a signal Location Estimator, and a peeling decoder that recovers aliased signals from a sparsely populated spectrum. A single-issue, in-order RISC-V Rocket processor interacts with the spectrum analyzer for post-processing and calibration. The ADC consumes 49.8mW with a 3.78-GHz input clock. At 400MHz and 0.7-V VDD, the Rocket core and the FFAST DSP together consume 133.5mW.
