The Experts below are selected from a list of 7782 Experts worldwide ranked by ideXlab platform
David Blaauw - One of the best experts on this subject based on the ideXlab platform.
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a 28 nm configurable memory tcam bcam sram using push rule 6t bit cell enabling logic in memory
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2–5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search Operations. In addition, the configurable memory can perform bit-wise Logical Operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and Logical function capability can be used to off-load specific computational Operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM bit cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/bit. A Logical Operation between two 64 bit words achieves 787 MHz at 1 V.
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A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory
IEEE Journal of Solid-State Circuits, 2016Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2-5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search Operations. In addition, the configurable memory can perform bit-wise Logical Operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and Logical function capability can be used to off-load specific computational Operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM bit cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/bit. A Logical Operation between two 64 bit words achieves 787 MHz at 1 V.
Supreet Jeloka - One of the best experts on this subject based on the ideXlab platform.
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a 28 nm configurable memory tcam bcam sram using push rule 6t bit cell enabling logic in memory
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2–5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search Operations. In addition, the configurable memory can perform bit-wise Logical Operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and Logical function capability can be used to off-load specific computational Operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM bit cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/bit. A Logical Operation between two 64 bit words achieves 787 MHz at 1 V.
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A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory
IEEE Journal of Solid-State Circuits, 2016Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2-5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search Operations. In addition, the configurable memory can perform bit-wise Logical Operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and Logical function capability can be used to off-load specific computational Operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM bit cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/bit. A Logical Operation between two 64 bit words achieves 787 MHz at 1 V.
Dennis Sylvester - One of the best experts on this subject based on the ideXlab platform.
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a 28 nm configurable memory tcam bcam sram using push rule 6t bit cell enabling logic in memory
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2–5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search Operations. In addition, the configurable memory can perform bit-wise Logical Operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and Logical function capability can be used to off-load specific computational Operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM bit cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/bit. A Logical Operation between two 64 bit words achieves 787 MHz at 1 V.
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A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory
IEEE Journal of Solid-State Circuits, 2016Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2-5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search Operations. In addition, the configurable memory can perform bit-wise Logical Operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and Logical function capability can be used to off-load specific computational Operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM bit cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/bit. A Logical Operation between two 64 bit words achieves 787 MHz at 1 V.
Naveen Bharathwaj Akesh - One of the best experts on this subject based on the ideXlab platform.
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a 28 nm configurable memory tcam bcam sram using push rule 6t bit cell enabling logic in memory
IEEE Journal of Solid-state Circuits, 2016Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2–5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search Operations. In addition, the configurable memory can perform bit-wise Logical Operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and Logical function capability can be used to off-load specific computational Operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM bit cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/bit. A Logical Operation between two 64 bit words achieves 787 MHz at 1 V.
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A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory
IEEE Journal of Solid-State Circuits, 2016Co-Authors: Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David BlaauwAbstract:Conventional content addressable memory (BCAM and TCAM) uses specialized 10T/16T bit cells that are significantly larger than 6T SRAM cells. A new BCAM/TCAM is proposed that can operate with standard push-rule 6T SRAM cells, reducing array area by 2-5× and allowing reconfiguration of the SRAM as a CAM. In this way, chip area and overall capacitance can be reduced, leading to higher energy efficiency for search Operations. In addition, the configurable memory can perform bit-wise Logical Operations: “AND” and “NOR” on two or more words stored within the array. Thus, the configurable memory with CAM and Logical function capability can be used to off-load specific computational Operations to the memory, improving system performance and efficiency. Using a 6T 28 nm FDSOI SRAM bit cell, the 64×64 (4 kb) BCAM achieves 370 MHz at 1 V and consumes 0.6 fJ/search/bit. A Logical Operation between two 64 bit words achieves 787 MHz at 1 V.
Aiguo Song - One of the best experts on this subject based on the ideXlab platform.
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set reset latch Logical Operation induced by colored noise
Physics Letters A, 2014Co-Authors: Nan Wang, Aiguo SongAbstract:Abstract We examine the possibility of obtaining Set–Reset latch Logical Operation in a symmetric bistable system subjected to OU noise. Three major results are presented. First, we prove the Set–Reset latch Logical Operation can be obtained driven by OU noise. Second, while increasing the correlation time, the optimal noise band shifts to higher level and becomes wider. Meanwhile, peak performance degrades from 100% accuracy, but the system can still perform reliable Logical Operation. Third, at fixed noise intensity, the success probability evolves non-monotonically as correlation time increases. The study might provide development of the new paradigm of memory device.
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Set–Reset latch Logical Operation induced by colored noise
Physics Letters A, 2014Co-Authors: Nan Wang, Aiguo SongAbstract:Abstract We examine the possibility of obtaining Set–Reset latch Logical Operation in a symmetric bistable system subjected to OU noise. Three major results are presented. First, we prove the Set–Reset latch Logical Operation can be obtained driven by OU noise. Second, while increasing the correlation time, the optimal noise band shifts to higher level and becomes wider. Meanwhile, peak performance degrades from 100% accuracy, but the system can still perform reliable Logical Operation. Third, at fixed noise intensity, the success probability evolves non-monotonically as correlation time increases. The study might provide development of the new paradigm of memory device.
