The Experts below are selected from a list of 1539 Experts worldwide ranked by ideXlab platform
I. Ouaiss - One of the best experts on this subject based on the ideXlab platform.
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DAC - An automated temporal partitioning and Loop Fission approach for FPGA based reconfigurable synthesis of DSP applications
Proceedings of the 36th ACM IEEE conference on Design automation conference - DAC '99, 1999Co-Authors: M. Kaul, R. Vemuri, S. Govindarajan, I. OuaissAbstract:We present an automated temporal partitioning and Loop transformation approach for developing dynamically reconfigurable designs starting from behavior level specifications. An Integer Linear Programming (ILP) model is formulated to achieve near-optimal latency designs. We, also present a Loop restructuring method to achieve maximum throughput for a class of DSP applications. This restructuring transformation is performed on the temporally partitioned behavior and results in near-optimization of throughput. We discuss efficient memory mapping and address generation techniques for the synthesis of reconfigurable designs. A case study on the Joint Photographic Experts Group (JPEG) image compression algorithm demonstrates the effectiveness of our approach.
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An automated temporal partitioning and Loop Fission approach for FPGA based reconfigurable synthesis of DSP applications
Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), 1Co-Authors: M. Kaul, R. Vemuri, S. Govindarajan, I. OuaissAbstract:We present an automated temporal partitioning and Loop transformation approach for developing dynamically reconfigurable designs starting from behavior level specifications. An Integer Linear Programming (ILP) model is formulated to achieve near-optimal latency designs. We, also present a Loop restructuring method to achieve maximum throughput for a class of DSP applications. This restructuring transformation is performed on the temporally partitioned behavior and results in near-optimization of throughput. We discuss efficient memory mapping and address generation techniques for the synthesis of reconfigurable designs. A case study on the Joint Photographic Experts Group (JPEG) image compression algorithm demonstrates the effectiveness of our approach.N/
M. Kaul - One of the best experts on this subject based on the ideXlab platform.
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DAC - An automated temporal partitioning and Loop Fission approach for FPGA based reconfigurable synthesis of DSP applications
Proceedings of the 36th ACM IEEE conference on Design automation conference - DAC '99, 1999Co-Authors: M. Kaul, R. Vemuri, S. Govindarajan, I. OuaissAbstract:We present an automated temporal partitioning and Loop transformation approach for developing dynamically reconfigurable designs starting from behavior level specifications. An Integer Linear Programming (ILP) model is formulated to achieve near-optimal latency designs. We, also present a Loop restructuring method to achieve maximum throughput for a class of DSP applications. This restructuring transformation is performed on the temporally partitioned behavior and results in near-optimization of throughput. We discuss efficient memory mapping and address generation techniques for the synthesis of reconfigurable designs. A case study on the Joint Photographic Experts Group (JPEG) image compression algorithm demonstrates the effectiveness of our approach.
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An automated temporal partitioning and Loop Fission approach for FPGA based reconfigurable synthesis of DSP applications
Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), 1Co-Authors: M. Kaul, R. Vemuri, S. Govindarajan, I. OuaissAbstract:We present an automated temporal partitioning and Loop transformation approach for developing dynamically reconfigurable designs starting from behavior level specifications. An Integer Linear Programming (ILP) model is formulated to achieve near-optimal latency designs. We, also present a Loop restructuring method to achieve maximum throughput for a class of DSP applications. This restructuring transformation is performed on the temporally partitioned behavior and results in near-optimization of throughput. We discuss efficient memory mapping and address generation techniques for the synthesis of reconfigurable designs. A case study on the Joint Photographic Experts Group (JPEG) image compression algorithm demonstrates the effectiveness of our approach.N/
S. Govindarajan - One of the best experts on this subject based on the ideXlab platform.
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DAC - An automated temporal partitioning and Loop Fission approach for FPGA based reconfigurable synthesis of DSP applications
Proceedings of the 36th ACM IEEE conference on Design automation conference - DAC '99, 1999Co-Authors: M. Kaul, R. Vemuri, S. Govindarajan, I. OuaissAbstract:We present an automated temporal partitioning and Loop transformation approach for developing dynamically reconfigurable designs starting from behavior level specifications. An Integer Linear Programming (ILP) model is formulated to achieve near-optimal latency designs. We, also present a Loop restructuring method to achieve maximum throughput for a class of DSP applications. This restructuring transformation is performed on the temporally partitioned behavior and results in near-optimization of throughput. We discuss efficient memory mapping and address generation techniques for the synthesis of reconfigurable designs. A case study on the Joint Photographic Experts Group (JPEG) image compression algorithm demonstrates the effectiveness of our approach.
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An automated temporal partitioning and Loop Fission approach for FPGA based reconfigurable synthesis of DSP applications
Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), 1Co-Authors: M. Kaul, R. Vemuri, S. Govindarajan, I. OuaissAbstract:We present an automated temporal partitioning and Loop transformation approach for developing dynamically reconfigurable designs starting from behavior level specifications. An Integer Linear Programming (ILP) model is formulated to achieve near-optimal latency designs. We, also present a Loop restructuring method to achieve maximum throughput for a class of DSP applications. This restructuring transformation is performed on the temporally partitioned behavior and results in near-optimization of throughput. We discuss efficient memory mapping and address generation techniques for the synthesis of reconfigurable designs. A case study on the Joint Photographic Experts Group (JPEG) image compression algorithm demonstrates the effectiveness of our approach.N/
R. Vemuri - One of the best experts on this subject based on the ideXlab platform.
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DAC - An automated temporal partitioning and Loop Fission approach for FPGA based reconfigurable synthesis of DSP applications
Proceedings of the 36th ACM IEEE conference on Design automation conference - DAC '99, 1999Co-Authors: M. Kaul, R. Vemuri, S. Govindarajan, I. OuaissAbstract:We present an automated temporal partitioning and Loop transformation approach for developing dynamically reconfigurable designs starting from behavior level specifications. An Integer Linear Programming (ILP) model is formulated to achieve near-optimal latency designs. We, also present a Loop restructuring method to achieve maximum throughput for a class of DSP applications. This restructuring transformation is performed on the temporally partitioned behavior and results in near-optimization of throughput. We discuss efficient memory mapping and address generation techniques for the synthesis of reconfigurable designs. A case study on the Joint Photographic Experts Group (JPEG) image compression algorithm demonstrates the effectiveness of our approach.
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An automated temporal partitioning and Loop Fission approach for FPGA based reconfigurable synthesis of DSP applications
Proceedings 1999 Design Automation Conference (Cat. No. 99CH36361), 1Co-Authors: M. Kaul, R. Vemuri, S. Govindarajan, I. OuaissAbstract:We present an automated temporal partitioning and Loop transformation approach for developing dynamically reconfigurable designs starting from behavior level specifications. An Integer Linear Programming (ILP) model is formulated to achieve near-optimal latency designs. We, also present a Loop restructuring method to achieve maximum throughput for a class of DSP applications. This restructuring transformation is performed on the temporally partitioned behavior and results in near-optimization of throughput. We discuss efficient memory mapping and address generation techniques for the synthesis of reconfigurable designs. A case study on the Joint Photographic Experts Group (JPEG) image compression algorithm demonstrates the effectiveness of our approach.N/
Ramin Yahyapour - One of the best experts on this subject based on the ideXlab platform.
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ICA3PP (Workshops) - A Practical and Aggressive Loop Fission Technique
Algorithms and Architectures for Parallel Processing, 2018Co-Authors: Bo Zhao, Lin Han, Jie Zhao, Wei Gao, Rongcai Zhao, Ramin YahyapourAbstract:Loop Fission is an effective Loop optimization for exploiting fine-grained parallelism. Currently, Loop Fission is widely used in existing parallelizing compilers. To fully exploit the optimization, we proposed and implemented a practical and aggressive Loop Fission technique. First, we present an aggressive dependence graph pruning method to eliminate pseudo dependences caused by the conservativeness of compilers. Second, we introduce a topological sort based Loop Fission algorithm to distribute Loops correctly. Finally, to enhance the performance of the generated programs which have potential of Loop Fission, we propose an advanced Loop Fission strategy. We evaluate these techniques and algorithms in the experimental section.
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a practical and aggressive Loop Fission technique
International Conference on Algorithms and Architectures for Parallel Processing, 2018Co-Authors: Bo Zhao, Lin Han, Jie Zhao, Wei Gao, Rongcai Zhao, Ramin YahyapourAbstract:Loop Fission is an effective Loop optimization for exploiting fine-grained parallelism. Currently, Loop Fission is widely used in existing parallelizing compilers. To fully exploit the optimization, we proposed and implemented a practical and aggressive Loop Fission technique. First, we present an aggressive dependence graph pruning method to eliminate pseudo dependences caused by the conservativeness of compilers. Second, we introduce a topological sort based Loop Fission algorithm to distribute Loops correctly. Finally, to enhance the performance of the generated programs which have potential of Loop Fission, we propose an advanced Loop Fission strategy. We evaluate these techniques and algorithms in the experimental section.
