The Experts below are selected from a list of 31041 Experts worldwide ranked by ideXlab platform
Tingting Hwang - One of the best experts on this subject based on the ideXlab platform.
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Thermal-aware Memory Mapping in 3D designs
ACM Transactions on Embedded Computing Systems, 2013Co-Authors: Ang-chih Hsieh, Tingting HwangAbstract:DRAM is usually used as main Memory for program execution. The thermal behavior of a Memory block in a 3D SIP is affected not only by the power behavior but also the heat dissipating ability of that block. The power behavior of a block is related to the applications run on the system, while the heat dissipating ability is determined by the number of tier and the position the block locates. Therefore, a thermal-aware Memory allocator should consider the following two points. First, the allocator should consider not only the power behavior of a logic block but also the physical location during Memory Mapping and second, the changing temperature of a physical block during execution of programs. In this article, we will propose a Memory Mapping algorithm taking into consideration these two points. Our technique can be classified as static thermal management to be applied to embedded software designs. Experiments show that for single-core systems, our method can reduce the temperature of Memory system by 17.1°C, as compared to a straightforward Mapping in the best case, and 13.3°C on average. For systems with four cores, the temperature reductions are 9.9°C and 11.6°C on average when L1 cache of each core is set to 4KB and 8KB, respectively.
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ICPP - Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms
2011 International Conference on Parallel Processing, 2011Co-Authors: Ang-chih Hsieh, Shau-yin Tseng, Tingting HwangAbstract:Many-core technology is proposed as a solution to improve the performance of modern computer systems. To obtain good performance on a many-core system, exploiting parallelism in arithmetic level is not enough. Due to the contention of shared hardware resource, the speedup ratio of a many-core system is usually much lower than the number of processor units. In this paper, the contention of shared Memory resource is addressed. An algorithm is developed to perform Memory Mapping and task scheduling for many-core systems. According to experimental results, the proposed algorithm can effectively improve the performance by 64.77% in average. 43.55X speedup ratio can be achieved when 48 processor units are activated. The performance loss ratio is less than 10%.
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DATE - Thermal-aware Memory Mapping in 3D designs
2009 Design Automation & Test in Europe Conference & Exhibition, 2009Co-Authors: Ang-chih Hsieh, Tingting HwangAbstract:DRAM is usually used as main Memory for program execution. The thermal behavior of a Memory block in a 3D SIP is affected not only by the power behavior but also the heat dissipating ability of that block. The power behavior of a block is related to the applications run on the system while the heat dissipating ability is determined by the number of tier and the position the block locates. Therefore, a thermal-aware Memory allocator should consider the following two points. First, allocator should consider not only the power behavior of a Memory block but also the physical location during Memory Mapping, second, the changing temperature of a physical block during execution of programs. In this paper, we will propose a Memory Mapping algorithm taking into consideration the above-mentioned two points. Our technique can be classified as static thermal management to be applied to embedded software designs. Experiments show that our method can reduce temperature of Memory system by 17.2°C as compared to a straightforward Mapping in the best case, and 13.4°C in average.
Ang-chih Hsieh - One of the best experts on this subject based on the ideXlab platform.
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Thermal-aware Memory Mapping in 3D designs
ACM Transactions on Embedded Computing Systems, 2013Co-Authors: Ang-chih Hsieh, Tingting HwangAbstract:DRAM is usually used as main Memory for program execution. The thermal behavior of a Memory block in a 3D SIP is affected not only by the power behavior but also the heat dissipating ability of that block. The power behavior of a block is related to the applications run on the system, while the heat dissipating ability is determined by the number of tier and the position the block locates. Therefore, a thermal-aware Memory allocator should consider the following two points. First, the allocator should consider not only the power behavior of a logic block but also the physical location during Memory Mapping and second, the changing temperature of a physical block during execution of programs. In this article, we will propose a Memory Mapping algorithm taking into consideration these two points. Our technique can be classified as static thermal management to be applied to embedded software designs. Experiments show that for single-core systems, our method can reduce the temperature of Memory system by 17.1°C, as compared to a straightforward Mapping in the best case, and 13.3°C on average. For systems with four cores, the temperature reductions are 9.9°C and 11.6°C on average when L1 cache of each core is set to 4KB and 8KB, respectively.
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ICPP - Memory Mapping and Task Scheduling Techniques for Computation Models of Image Processing on Many-Core Platforms
2011 International Conference on Parallel Processing, 2011Co-Authors: Ang-chih Hsieh, Shau-yin Tseng, Tingting HwangAbstract:Many-core technology is proposed as a solution to improve the performance of modern computer systems. To obtain good performance on a many-core system, exploiting parallelism in arithmetic level is not enough. Due to the contention of shared hardware resource, the speedup ratio of a many-core system is usually much lower than the number of processor units. In this paper, the contention of shared Memory resource is addressed. An algorithm is developed to perform Memory Mapping and task scheduling for many-core systems. According to experimental results, the proposed algorithm can effectively improve the performance by 64.77% in average. 43.55X speedup ratio can be achieved when 48 processor units are activated. The performance loss ratio is less than 10%.
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DATE - Thermal-aware Memory Mapping in 3D designs
2009 Design Automation & Test in Europe Conference & Exhibition, 2009Co-Authors: Ang-chih Hsieh, Tingting HwangAbstract:DRAM is usually used as main Memory for program execution. The thermal behavior of a Memory block in a 3D SIP is affected not only by the power behavior but also the heat dissipating ability of that block. The power behavior of a block is related to the applications run on the system while the heat dissipating ability is determined by the number of tier and the position the block locates. Therefore, a thermal-aware Memory allocator should consider the following two points. First, allocator should consider not only the power behavior of a Memory block but also the physical location during Memory Mapping, second, the changing temperature of a physical block during execution of programs. In this paper, we will propose a Memory Mapping algorithm taking into consideration the above-mentioned two points. Our technique can be classified as static thermal management to be applied to embedded software designs. Experiments show that our method can reduce temperature of Memory system by 17.2°C as compared to a straightforward Mapping in the best case, and 13.4°C in average.
Eric Martin - One of the best experts on this subject based on the ideXlab platform.
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Memory Aware High-Level Synthesis for Embedded Systems
arXiv: Hardware Architecture, 2006Co-Authors: Gwenole Corre, Eric Senn, Nathalie Julien, Eric MartinAbstract:We introduce a new approach to take into account the Memory architecture and the Memory Mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the Memory Mapping as a set of constraints used in the scheduling step. We use a Memory Mapping file to include those Memory constraints in our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time. Finally, we show how to explore, with the help of GAUT, a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.
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A Memory Aware High Level Synthesis Too
arXiv: Hardware Architecture, 2006Co-Authors: Gwenole Corre, Eric Senn, Nathalie Julien, Eric MartinAbstract:We introduce a new approach to take into account the Memory architecture and the Memory Mapping in High- Level Synthesis for data intensive applications. We formalize the Memory Mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a Memory Mapping file to include those Memory constraints in our HLS tool GAUT. It is possible, with the help of GAUT, to explore a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.
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DSD - Memory aware HLS and the implementation of ageing vectors
2004Co-Authors: Gwenole Corre, Eric Senn, Nathalie Julien, Eric MartinAbstract:We introduce a new approach to take into account the Memory architecture and the Memory Mapping in behavioral synthesis. We formalize the Memory Mapping as a set of constraints for the synthesis, and defined a Memory constraint graph and an accessibility criterion to be used in the scheduling step. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate Memory conflicts over several iterations of the algorithm. The final compatibility graph indicates the set of valid Mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time.
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A Memory Aware High Level Synthesis Tool
2004Co-Authors: Gwenole Corre, Eric Senn, Nathalie Julien, Eric MartinAbstract:We introduce a new approach to take into account the Memory architecture and the Memory Mapping in High- Level Synthesis for data intensive applications. We formalize the Memory Mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a Memory Mapping file to include those Memory constraints in our HLS tool GAUT. It is possible, with the help of GAUT, to explore a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.
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ACM Great Lakes Symposium on VLSI - A Memory aware behavioral synthesis tool for real-time VLSI circuits
Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04, 2004Co-Authors: Gwenole Corre, Eric Senn, Nathalie Julien, Eric MartinAbstract:We introduce a new approach to take into account the Memory architecture and the Memory Mapping in the Behavioral Synthesis of Real-Time VLSI circuits. We formalize the Memory Mapping as a set of constraints for the thesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a Memory Mapping file to include those Memory straints in our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time. Several experiments are performed to demonstrate the efficiency of our method, and to compare GAUT with an industrial behavioral synthesis tool. We finally show how to explore, with the help of GAUT, a wide range of solutions, and to reach a good tradeoffs between time, power-consumption, and area.
Gwenole Corre - One of the best experts on this subject based on the ideXlab platform.
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Memory Aware High-Level Synthesis for Embedded Systems
arXiv: Hardware Architecture, 2006Co-Authors: Gwenole Corre, Eric Senn, Nathalie Julien, Eric MartinAbstract:We introduce a new approach to take into account the Memory architecture and the Memory Mapping in the High- Level Synthesis of Real-Time embedded systems. We formalize the Memory Mapping as a set of constraints used in the scheduling step. We use a Memory Mapping file to include those Memory constraints in our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time. Finally, we show how to explore, with the help of GAUT, a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.
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A Memory Aware High Level Synthesis Too
arXiv: Hardware Architecture, 2006Co-Authors: Gwenole Corre, Eric Senn, Nathalie Julien, Eric MartinAbstract:We introduce a new approach to take into account the Memory architecture and the Memory Mapping in High- Level Synthesis for data intensive applications. We formalize the Memory Mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a Memory Mapping file to include those Memory constraints in our HLS tool GAUT. It is possible, with the help of GAUT, to explore a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.
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DSD - Memory aware HLS and the implementation of ageing vectors
2004Co-Authors: Gwenole Corre, Eric Senn, Nathalie Julien, Eric MartinAbstract:We introduce a new approach to take into account the Memory architecture and the Memory Mapping in behavioral synthesis. We formalize the Memory Mapping as a set of constraints for the synthesis, and defined a Memory constraint graph and an accessibility criterion to be used in the scheduling step. We present a new strategy for implementing signals (ageing vectors). We formalize the maturing process and explain how it may generate Memory conflicts over several iterations of the algorithm. The final compatibility graph indicates the set of valid Mappings for every signal. Several experiments are performed with our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time.
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A Memory Aware High Level Synthesis Tool
2004Co-Authors: Gwenole Corre, Eric Senn, Nathalie Julien, Eric MartinAbstract:We introduce a new approach to take into account the Memory architecture and the Memory Mapping in High- Level Synthesis for data intensive applications. We formalize the Memory Mapping as a set of constraints for the synthesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a Memory Mapping file to include those Memory constraints in our HLS tool GAUT. It is possible, with the help of GAUT, to explore a wide range of solutions, and to reach a good tradeoff between time, power-consumption, and area.
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ACM Great Lakes Symposium on VLSI - A Memory aware behavioral synthesis tool for real-time VLSI circuits
Proceedins of the 14th ACM Great Lakes symposium on VLSI - GLSVLSI '04, 2004Co-Authors: Gwenole Corre, Eric Senn, Nathalie Julien, Eric MartinAbstract:We introduce a new approach to take into account the Memory architecture and the Memory Mapping in the Behavioral Synthesis of Real-Time VLSI circuits. We formalize the Memory Mapping as a set of constraints for the thesis, and defined a Memory Constraint Graph and an accessibility criterion to be used in the scheduling step. We use a Memory Mapping file to include those Memory straints in our HLS tool GAUT. Our scheduling algorithm exhibits a relatively low complexity that permits to tackle complex designs in a reasonable time. Several experiments are performed to demonstrate the efficiency of our method, and to compare GAUT with an industrial behavioral synthesis tool. We finally show how to explore, with the help of GAUT, a wide range of solutions, and to reach a good tradeoffs between time, power-consumption, and area.
Ranga Vemuri - One of the best experts on this subject based on the ideXlab platform.
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Hierarchical Memory synthesis in reconfigurable computers
2002Co-Authors: Iyad Ouaiss, Ranga VemuriAbstract:A Reconfigurable Computer (RC) is a hardware platform that typically includes several programmable devices, Memory devices, and possibly specialized devices such as analog-to-digital converters. Such high-performance platforms are capable of accommodating large designs while avoiding the time-to-market associated with ASIC implementations. This work addresses the process of Mapping data structures of an application onto the storage elements of RCs with hierarchical memories. In order to optimize the placement of data, several aspects of data Mapping are addressed. Input specification styles and synthesis-related issues, physical resource conflicts and arbitration issues, several Memory Mapping techniques, and interaction between Memory Mapping and logic partitioning are presented and discussed. The state-of-the-art in reconfigurable computers and their Memory subsystems is reviewed and RCs are classified based on their architectures. The importance of hierarchical memories in RCs and the trend in increasing complexity is discussed. A specification model that is well-suited for the Memory Mapping problem is introduced and the synthesis mechanism involved is described. Several Memory Mapping techniques are presented and their applicability on existing hardware platforms is discussed. Integer Linear Programming (ILP) formulations are used and assignment techniques that cater to different RC features are developed. With this technique, small to medium sized designs are solved in a reasonable amount of time. Furthermore, these solutions are optimal. On the other hand, with large sized designs, these ILP techniques become time consuming. Because of their slow execution speed and the complexity of the problem, a novel methodology that speeds up the execution while retaining a high Mapping quality is introduced. This methodology divides the Mapping process into two, global/detailed, sequential steps (ILP-based) and produces fast Mappings at a relatively small quality cost. One important issue when dealing with the Memory assignment problem is resource conflicts. If the number of physical memories on the RC is limited, the assignment is forced to reuse these resources thus creating access conflicts. This problem is presented and an efficient arbitration solution that is well-suited for RC environments is proposed and implemented. Finally, Memory Mapping techniques are extended to interface with logic partitioning tools. A full spatial partitioning framework is presented where Memory Mapping interacts with logic partitioning and optimizes the overall placement of both computations as well as data in the design.
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FPL - Memory Synthesis for FPGA-Based Reconfigurable Computers
Field-Programmable Logic and Applications, 2001Co-Authors: Amit Kasat, Iyad Ouaiss, Ranga VemuriAbstract:For data intensive applications like Digital Signal Processing, Image Processing, and Pattern Recognition, Memory reads and writes constitute a large portion of the total design execution time. With the advent of on-chip memories, a rich hierarchy of physical memories is now available on a Reconfigurable Computer (RC). An intelligent usage of these memories can lead to a significant improvement in the latency of the overall design. This paper presents an automated heuristic-based Memory Mapping framework for RCs. We use a Tabu search guided heuristic, Rectangle Carving, to map a single data structure onto several instances of a Memory type on the RC. We also introduce control logic to resolve potential Memory access conflicts and to make the details of Memory Mapping transparent to the accessing logic.
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Memory synthesis for FPGA-based Reconfigurable computers
Lecture Notes in Computer Science, 2001Co-Authors: Amit Kasat, Iyad Ouaiss, Ranga VemuriAbstract:For data intensive applications like Digital Signal Processing, Image Processing, and Pattern Recognition, Memory reads and writes constitute a large portion of the total design execution time, With the advent of on-chip memories, a rich hierarchy of physical memories is now available on a Reconfigurable Computer (RC). An intelligent usage of these memories can lead to a significant improvement in the latency of the overall design. This paper presents an automated heuristic-based Memory Mapping framework for RCs. We use a Tabu search guided heuristic, Rectangle Carving, to map a single data structure onto several instances of a Memory type on the RC. We also introduce control logic to resolve potential Memory access conflicts and to make the details of Memory Mapping transparent to the accessing logic.
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IPDPS - Global Memory Mapping for FPGA-based reconfigurable systems
Proceedings 15th International Parallel and Distributed Processing Symposium. IPDPS 2001, 1Co-Authors: Iyad Ouaiss, Ranga VemuriAbstract:Synthesizing designs for FPGA-based reconfigurable systems involves the task of Mapping variables and data structures of the application onto RAMs of the reconfigurable board. The variety in types and performance of onboard and on-chip RAMs, their proximity to the processing units, and the interconnection scheme of the reconfigurable system, all contribute to an intricate Memory Mapping problem. An intelligent Memory assignment minimizes the total latency of the design and the interconnection requirements due to Memory accesses. A complete Integer Linear Programming (ILP) formulation of the problem results in an optimized Memory Mapping; however, the formulation is complex and takes a very long time to produce a solution. In order to efficiently solve the problem, the concept of global/detailed Memory Mapping is introduced in this paper. An ILP formulation of the global Mapping process is described. This formulation is simpler and faster than the complete formulation, and it leaves the task of detailed Mapping to a post-ILP tool that does not affect the optimality of the Memory assignment. As a result, larger designs can be handled at a faster rate and more constraints can be introduced to the formulation.
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DATE - Hierarchical Memory Mapping during synthesis in FPGA-based reconfigurable computers
Proceedings Design Automation and Test in Europe. Conference and Exhibition 2001, 1Co-Authors: Iyad Ouaiss, Ranga VemuriAbstract:One step in the synthesis for FPGA-based Reconfigurable Computers (RCs) involves Mapping the design data structures onto the physical Memory banks available in the hardware. The advent of Xilinx Virtex-style FPGAs and of hierarchical Memory schemes on reconfigurable boards introduced an added complexity to this Mapping. The new RC boards offer a wealth of Memory banks many of them on-chip (such as the BlockRAMs available in the Virtex architecture) and many of them offering variable number of ports and several depth/width configurations. Along with the external RAMs, a hierarchy of memories with varying access performances are available in a reconfigurable computer. It becomes critical to perform a good Mapping to achieve optimal design performance. This paper presents an automatic Memory Mapping methodology which takes into account: the number of words and word size of design data segments and physical Memory banks, number of ports on the banks, access latency of the banks, proximity of the banks to the processing unit, life cycle analysis of data segments, and it also incorporates configuration selection from the multiple configurations available in BlockRAMs of Virtex series FPGAs. In the case of multiple processing elements on board, the paper also provides a framework in which the task of Memory Mapping interacts with spatial partitioning to provide the best implementation.