The Experts below are selected from a list of 7989 Experts worldwide ranked by ideXlab platform
Jing-wen Hwang - One of the best experts on this subject based on the ideXlab platform.
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Low-Power Design for Real-Time Systems
Real-Time Systems, 1998Co-Authors: Sheng-tzong Cheng, Chia-mei Chen, Jing-wen HwangAbstract:Real-time Systems often are located in the special environments where the power consumption is a big concern. Upon presence of timing constraints, the low power Design on the real-time systems has significant impact on the performance as well as the schedulability of the systems. The system developers are facing the challenges for reducing the power consumption and meeting the timing constraints in the real-time systems. This paper represents one of few attempts to address the issue of the low power Design on real-time systems. We present two power reduction methods: one is at the software compilation level and the other at the operating system level. Given a real-time program, an inter-instruction power reduction technique is proposed to transform the program to another one with lower power consumption. In addition, a scheduling algorithm for real-time operating systems is proposed to reschedule real-time programs when the execution time of the programs is changed. Therefore, the proposed scheduling algorithm works together with the proposed power reduction technique to make sure all programs meet their deadlines and to improve the system schedulability. We also evaluate the performance of the proposed inter-instruction reduction method by comparing it with the cold scheduling algorithm and show that the proposed method outperforms the cold scheduling algorithm and reduces more energy power.
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Low-Power Design for real-time systems
Real-Time Systems, 1998Co-Authors: Sheng-tzong Cheng, Chia-mei Chen, Jing-wen HwangAbstract:This paper addresses the issue of low power Design for real-time systems. We present a power reduction method at the software compilation level. Given a real-time program, an inter-instruction power reduction technique is proposed to transform the program to another one with lower power consumption. In addition, a scheduling algorithm for real-time operating systems is proposed to reschedule real-time programs when the execution time of the programs is changed. Therefore, the proposed scheduling algorithm works together with the proposed power reduction technique to make sure all programs meet their deadlines and to improve the system schedulability. We also evaluate the performance of the proposed inter-instruction reduction method by comparing it with the cold scheduling algorithm and show that the proposed method outperforms the cold scheduling algorithm and reduces more energy power.
Chen-yi Lee - One of the best experts on this subject based on the ideXlab platform.
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A Low-Power Design FOR REED-SOLOMON DECODERS
Journal of Circuits Systems and Computers, 2003Co-Authors: Hsie-chia Chang, Chen-yi LeeAbstract:In this paper, a Low-Power Design for the Reed–Solomon (RS) decoder is presented. Our approach includes a novel two-stage syndrome calculator that reduces the syndrome computations by one-half, a modified Berlekamp–Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The test chip for (255,239) and (208,192) RS decoders are implemented by 0.25 μm CMOS 1P5M and 0.35 μm CMOS SPQM standard cells, respectively. Simulation results show our approach can work successfully and achieved large reduction of power consumption on the average.
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A Low-Power Design for Reed–Solomon Decoders
Journal of Circuits Systems and Computers, 2003Co-Authors: Hsie-chia Chang, Chen-yi LeeAbstract:In this paper, a Low-Power Design for the Reed–Solomon (RS) decoder is presented. Our approach includes a novel two-stage syndrome calculator that reduces the syndrome computations by one-half, a modified Berlekamp–Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The test chip for (255,239) and (208,192) RS decoders are implemented by 0.25 μm CMOS 1P5M and 0.35 μm CMOS SPQM standard cells, respectively. Simulation results show our approach can work successfully and achieved large reduction of power consumption on the average.
Sheng-tzong Cheng - One of the best experts on this subject based on the ideXlab platform.
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Low-Power Design for Real-Time Systems
Real-Time Systems, 1998Co-Authors: Sheng-tzong Cheng, Chia-mei Chen, Jing-wen HwangAbstract:Real-time Systems often are located in the special environments where the power consumption is a big concern. Upon presence of timing constraints, the low power Design on the real-time systems has significant impact on the performance as well as the schedulability of the systems. The system developers are facing the challenges for reducing the power consumption and meeting the timing constraints in the real-time systems. This paper represents one of few attempts to address the issue of the low power Design on real-time systems. We present two power reduction methods: one is at the software compilation level and the other at the operating system level. Given a real-time program, an inter-instruction power reduction technique is proposed to transform the program to another one with lower power consumption. In addition, a scheduling algorithm for real-time operating systems is proposed to reschedule real-time programs when the execution time of the programs is changed. Therefore, the proposed scheduling algorithm works together with the proposed power reduction technique to make sure all programs meet their deadlines and to improve the system schedulability. We also evaluate the performance of the proposed inter-instruction reduction method by comparing it with the cold scheduling algorithm and show that the proposed method outperforms the cold scheduling algorithm and reduces more energy power.
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Low-Power Design for real-time systems
Real-Time Systems, 1998Co-Authors: Sheng-tzong Cheng, Chia-mei Chen, Jing-wen HwangAbstract:This paper addresses the issue of low power Design for real-time systems. We present a power reduction method at the software compilation level. Given a real-time program, an inter-instruction power reduction technique is proposed to transform the program to another one with lower power consumption. In addition, a scheduling algorithm for real-time operating systems is proposed to reschedule real-time programs when the execution time of the programs is changed. Therefore, the proposed scheduling algorithm works together with the proposed power reduction technique to make sure all programs meet their deadlines and to improve the system schedulability. We also evaluate the performance of the proposed inter-instruction reduction method by comparing it with the cold scheduling algorithm and show that the proposed method outperforms the cold scheduling algorithm and reduces more energy power.
Hsie-chia Chang - One of the best experts on this subject based on the ideXlab platform.
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A Low-Power Design FOR REED-SOLOMON DECODERS
Journal of Circuits Systems and Computers, 2003Co-Authors: Hsie-chia Chang, Chen-yi LeeAbstract:In this paper, a Low-Power Design for the Reed–Solomon (RS) decoder is presented. Our approach includes a novel two-stage syndrome calculator that reduces the syndrome computations by one-half, a modified Berlekamp–Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The test chip for (255,239) and (208,192) RS decoders are implemented by 0.25 μm CMOS 1P5M and 0.35 μm CMOS SPQM standard cells, respectively. Simulation results show our approach can work successfully and achieved large reduction of power consumption on the average.
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A Low-Power Design for Reed–Solomon Decoders
Journal of Circuits Systems and Computers, 2003Co-Authors: Hsie-chia Chang, Chen-yi LeeAbstract:In this paper, a Low-Power Design for the Reed–Solomon (RS) decoder is presented. Our approach includes a novel two-stage syndrome calculator that reduces the syndrome computations by one-half, a modified Berlekamp–Massey algorithm in the key equation solver and a terminated mechanism in the Chien search circuit. The test chip for (255,239) and (208,192) RS decoders are implemented by 0.25 μm CMOS 1P5M and 0.35 μm CMOS SPQM standard cells, respectively. Simulation results show our approach can work successfully and achieved large reduction of power consumption on the average.
Shayan Taheri - One of the best experts on this subject based on the ideXlab platform.
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Ultra-Low-Power Design and Hardware Security Using Emerging Technologies for Internet of Things
Electronics, 2017Co-Authors: Jiann-shiun Yuan, Jie Lin, Qutaiba Alasad, Shayan TaheriAbstract:In this review article for Internet of Things (IoT) applications, important Low-Power Design techniques for digital and mixed-signal analog–digital converter (ADC) circuits are presented. Emerging low voltage logic devices and non-volatile memories (NVMs) beyond CMOS are illustrated. In addition, energy-constrained hardware security issues are reviewed. Specifically, light-weight encryption-based correlational power analysis, successive approximation register (SAR) ADC security using tunnel field effect transistors (FETs), logic obfuscation using silicon nanowire FETs, and all-spin logic devices are highlighted. Furthermore, a novel ultra-low power Design using bio-inspired neuromorphic computing and spiking neural network security are discussed.
