The Experts below are selected from a list of 216 Experts worldwide ranked by ideXlab platform

A. Orailoglu - One of the best experts on this subject based on the ideXlab platform.

  • Scan power minimization through stimulus and response transformations
    Proceedings Design Automation and Test in Europe Conference and Exhibition, 2004
    Co-Authors: O. Sinanoglu, A. Orailoglu
    Abstract:

    Scan-based cores impose considerable test power challenges due to excessive switching activity during shift cycles. The consequent test power constraints force SOC designers to sacrifice parallelism among core tests, as exceeding power thresholds may damage the chip being tested. Reduction of test power for SOC cores can thus increase the number of cores that can be tested in parallel, improving significantly SOC test application time. In this paper, we propose a scan chain modification technique that inserts logic gates on the scan path. The consequent beneficial test data transformations are utilized to reduce the scan chain transitions during shift cycles and hence test power. We introduce a Matrix Band algebra that models the impact of logic gate insertion between scan cells on the test stimulus and response transformations realized. As we have successfully modeled the response transformations as well, the methodology we propose is capable of truly minimizing the overall test power. The test vectors and responses are analyzed in an intertwined manner, identifying the best possible scan chain modification, which is realized at minimal area cost. Experimental results justify the efficacy of the proposed methodology as well.

  • ICCD - Aggressive test power reduction through test stimuli transformation
    Proceedings 21st International Conference on Computer Design, 2003
    Co-Authors: O. Sinanoglu, A. Orailoglu
    Abstract:

    Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain modification methodology that transforms the stimuli to be inserted to the scan chain through logic gate insertion between scan cells, reducing scan chain transitions. We introduce a novel Matrix Band algebra to formulate the impact of scan chain modifications on test stimuli transformations. Based on this analysis, we develop algorithms for transforming a set of test vectors into power-optimal test stimuli through cost-effective scan chain modifications. Experimental results show that scan-in power reductions exceeding 90% for test vectors and 99.5% for test cubes can be attained by the proposed methodology.

  • Aggressive test power reduction through test stimuli transformation
    Proceedings 21st International Conference on Computer Design, 2003
    Co-Authors: O. Sinanoglu, A. Orailoglu
    Abstract:

    Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain modification methodology that transforms the stimuli to be inserted to the scan chain through logic gate insertion between scan cells, reducing scan chain transitions. We introduce a novel Matrix Band algebra to formulate the impact of scan chain modifications on test stimuli transformations. Based on this analysis, we develop algorithms for transforming a set of test vectors into power-optimal test stimuli through cost-effective scan chain modifications. Experimental results show that scan-in power reductions exceeding 90% for test vectors and 99.5% for test cubes can be attained by the proposed methodology.

O. Sinanoglu - One of the best experts on this subject based on the ideXlab platform.

  • Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations
    Journal of Electronic Testing, 2008
    Co-Authors: O. Sinanoglu
    Abstract:

    Scan-based cores impose considerable test power challenges due to excessive switching activity during shift cycles. The consequent test power constraints force system-on-chip (SOC) designers to sacrifice parallelism among core tests, as exceeding power thresholds may damage the chip being tested. Reduction of test power for SOC cores can thus increase the number of cores that can be tested in parallel, improving significantly SOC test application time. In this paper, we propose a scan chain modification technique that inserts logic gates on the scan path. The consequent beneficial test data transformations are utilized to reduce the scan chain transitions during shift cycles and hence test power. We introduce a Matrix Band algebra that models the impact of logic gate insertion between scan cells on the test stimulus and response transformations realized. As we have successfully modeled the response transformations as well, the methodology we propose is capable of truly minimizing the overall test power. The test vectors and responses are analyzed in an intertwined manner, identifying the best possible scan chain modification, which is realized at minimal area cost. Experimental results justify the efficacy of the proposed methodology as well.

  • Scan power minimization through stimulus and response transformations
    Proceedings Design Automation and Test in Europe Conference and Exhibition, 2004
    Co-Authors: O. Sinanoglu, A. Orailoglu
    Abstract:

    Scan-based cores impose considerable test power challenges due to excessive switching activity during shift cycles. The consequent test power constraints force SOC designers to sacrifice parallelism among core tests, as exceeding power thresholds may damage the chip being tested. Reduction of test power for SOC cores can thus increase the number of cores that can be tested in parallel, improving significantly SOC test application time. In this paper, we propose a scan chain modification technique that inserts logic gates on the scan path. The consequent beneficial test data transformations are utilized to reduce the scan chain transitions during shift cycles and hence test power. We introduce a Matrix Band algebra that models the impact of logic gate insertion between scan cells on the test stimulus and response transformations realized. As we have successfully modeled the response transformations as well, the methodology we propose is capable of truly minimizing the overall test power. The test vectors and responses are analyzed in an intertwined manner, identifying the best possible scan chain modification, which is realized at minimal area cost. Experimental results justify the efficacy of the proposed methodology as well.

  • ICCD - Aggressive test power reduction through test stimuli transformation
    Proceedings 21st International Conference on Computer Design, 2003
    Co-Authors: O. Sinanoglu, A. Orailoglu
    Abstract:

    Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain modification methodology that transforms the stimuli to be inserted to the scan chain through logic gate insertion between scan cells, reducing scan chain transitions. We introduce a novel Matrix Band algebra to formulate the impact of scan chain modifications on test stimuli transformations. Based on this analysis, we develop algorithms for transforming a set of test vectors into power-optimal test stimuli through cost-effective scan chain modifications. Experimental results show that scan-in power reductions exceeding 90% for test vectors and 99.5% for test cubes can be attained by the proposed methodology.

  • Aggressive test power reduction through test stimuli transformation
    Proceedings 21st International Conference on Computer Design, 2003
    Co-Authors: O. Sinanoglu, A. Orailoglu
    Abstract:

    Excessive switching activity during shift cycles in scan-based cores imposes considerable test power challenges. To ensure rapid and reliable test of SOCs, we propose a scan chain modification methodology that transforms the stimuli to be inserted to the scan chain through logic gate insertion between scan cells, reducing scan chain transitions. We introduce a novel Matrix Band algebra to formulate the impact of scan chain modifications on test stimuli transformations. Based on this analysis, we develop algorithms for transforming a set of test vectors into power-optimal test stimuli through cost-effective scan chain modifications. Experimental results show that scan-in power reductions exceeding 90% for test vectors and 99.5% for test cubes can be attained by the proposed methodology.

Simone Deliperi - One of the best experts on this subject based on the ideXlab platform.

  • Modified Matrix Band design for ultra-conservative posterior restorations.
    Operative dentistry, 2008
    Co-Authors: Simone Deliperi
    Abstract:

    Conventional box preparations, tunnel cavities and slot preparations have been recommended for the treatment of proximal carious lesions over the years. If the adjacent tooth is missing or the proximal surface becomes accessible at the time of cavity preparation of the adjacent tooth, a direct proximal access to the decay process can be performed. A similar procedure is supported by the use of adhesive composite restorations reinforcing the remaining sound tooth structure. The increasing patient and clinician's desire for ultraconservative treatment justifies this minimally invasive tooth preparation approach; however, appropriate materials and techniques need to be selected to achieve adequate bonding of the cavity walls and marginal adaptation of the composite.

  • Modified Matrix Band Design for Ultra-conservative Posterior Restorations
    Operative Dentistry, 2008
    Co-Authors: Simone Deliperi
    Abstract:

    Clinical Relevance The combination of minimally invasive cavity preparations and adhesive restorations allows clinicians a significantly more conservative approach to proximal carious lesions of teeth adjacent to MO/DO preparations.

William W. Brackett - One of the best experts on this subject based on the ideXlab platform.

H A Preisig - One of the best experts on this subject based on the ideXlab platform.

  • efficient numerical solver for partially structured differential and algebraic equation systems
    Industrial & Engineering Chemistry Research, 2009
    Co-Authors: Flavio Manenti, Ivan Dones, Guido Buzziferraris, H A Preisig
    Abstract:

    Given a sparse set of differential and algebraic equations (DAEs), it is always recommended to exploit the structure of the system’s sparsity (e.g., tridiagonal blocks Matrix, Band Matrix, and staircase Matrix, etc.), thus to use tailored numerical solvers in order to reduce the computation time. Very frequently, though, while highly structured, a couple of elements enter the description which make it difficult for the solvers to reach a solution. They are common in process control applications, where the states added to the plant description by the integral parts of the controllers introduce unstructured elements in the otherwise very structured Jacobian of the mathematical model. Such systems are characterized by a partially structured Jacobian, which inhibits the use of the solvers tailored to fit problems with fully structured matrices. In such cases, one can either use a solver with lower performance, resulting in larger computation times, or alternatively one seeks an approximation for the unstructu...