The Experts below are selected from a list of 360 Experts worldwide ranked by ideXlab platform
Yu Huang - One of the best experts on this subject based on the ideXlab platform.
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diagnosis of intermittent Scan Chain faults through a multistage neural network reasoning process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020Co-Authors: Mason Chern, Yu Huang, Shihwei Lee, Shiyu Huang, Gaurav Veda, Kunhan Tsai, Wutung ChengAbstract:Diagnosis of intermittent Scan Chain failures still remains a hard problem. In this article, we demonstrate that the use of artificial neural networks (ANNs) can lead to significantly higher accuracy. The key of this method is a multistage process incorporating ANNs with gradually refined focuses. During this process, the final fault suspect is elected through multiple rounds of ANN inference, instead of just one round. At each stage, identification of a proper Affine Group , used as the “candidate set of Scan cells for the next round of ANN inference,” will influence the final diagnostic accuracy. Thus, we propose a validation-based learning procedure for Affine Group derivation to further boost the final diagnostic accuracy. The experimental results on benchmark circuits have shown that this method is, on the average, 17.46% more accurate than a state-of-the-art commercial tool for intermittent stuck-at-0 faults.
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non adaptive pattern reordering to improve Scan Chain diagnostic resolution
European Test Symposium, 2019Co-Authors: Yu Huang, Jakub Janicki, Szczepan UrbanAbstract:All Automatic Test Equipment (ATEs) have fail buffer capacity limit, and the limited amount of collected failure data during testing has big negative impact on Scan Chain diagnostic resolutions. In the past, adaptive pattern reordering algorithms were proposed to improve the Scan Chain diagnostic resolutions. However in reality, either many ATEs do not support the proposed adaptive testing flows without additional test cost or the test engineers do not know how to program the ATEs to implement the proposed adaptive testing flows. Therefore, as far as we know, all of prior proposed adaptive testing flows are not applied in the real world yet. In this paper, we propose a non-adaptive pattern reordering flow to improve the Scan Chain diagnostic resolution, which can be readily applied in the current manufacture testing and volume diagnosis environment.
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Scan Chain diagnosis based on unsupervised machine learning
Asian Test Symposium, 2017Co-Authors: Yu Huang, B Benware, Randy Klingenberg, Huaxing Tang, Jayant Dsouza, Wutung ChengAbstract:Scan-based testing has proven to be a cost-effective method for achieving good test coverage in digital circuits. It was reported in prior papers that about 30% to 50% of all failing die were due to defects that cause Scan Chains to fail [1][2]. Therefore, Scan Chain failure diagnosis is very important to improve yield. The previously proposed methods of Chain diagnosis were primarily based on either deterministic fault models and simulation algorithms or probabilistic analysis. To handle hard-to-model defect behaviors more robustly, in this paper, we propose a new Scan Chain diagnosis algorithm based on unsupervised machine learning. Its application on "Scannable memory designs" (SMD) is demonstrated to illustrate the effectiveness of the proposed algorithm.
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diagnosis and layout aware dla Scan Chain stitching
IEEE Transactions on Very Large Scale Integration Systems, 2015Co-Authors: Yu Huang, Wutung Cheng, Ruifeng Guo, Liyang Lai, Tingpu Tai, Weipin Changchien, Dawming Lee, Jijan Chen, Sandeep C Eruvathi, Kartik K KumaraAbstract:Without appropriate stitching of Scan Chains, even with good diagnosis algorithm and diagnostic pattern generation, the Chain diagnostic resolution may still be bad. In this paper, we propose a novel pattern-independent diagnosis and layout aware (DLA) Scan Chain stitching method: 1) the resolution is improved by increasing and properly distributing the sensitive Scan cells, which can capture useful diagnostic information under both single- and multiple-fault situations; and 2) the Scan cell layout placement is taken into account to reduce routing overhead and hence preserve the chip performance. Experiments using two different techniques to diagnose ISCAS'89/ITC'99 benchmark circuits with/without embedded Scan compaction show the effectiveness of the proposed method in improving the diagnostic resolution. Impacts on chip performance, embedded Scan compaction, transition fault coverage, and test power dissipation are negligible. The proposed method is also successfully applied to an industry circuit manufactured with 20-nm technology. The silicon results show $7\times$ average resolution improvement comparing to without using the DLA Scan Chain stitching.
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diagnosis and layout aware dla Scan Chain stitching
International Test Conference, 2013Co-Authors: Yu Huang, Wutung Cheng, Ruifeng Guo, Liyang Lai, Tingpu Tai, Weipin Changchien, Dawming Lee, Jijan Chen, Sandeep C Eruvathi, Kartik K KumaraAbstract:Without appropriate stitching of Scan Chains, even with good diagnosis algorithm and diagnostic pattern generation, it may still result in bad Scan Chain diagnostic resolution. To improve the diagnostic resolution, we propose a novel Diagnosis and Layout Aware (DLA) Scan Chain stitching method, which is pattern independent and supports embedded Scan compaction. It is based on three ideas: (1) increasing the number of sensitive Scan cells, which can capture useful diagnostic information; (2) properly distributing the sensitive Scan cells along the Scan Chains to enhance the overall resolution; (3) stitching Scan cells based on their placement at layout to preserve the chip performance. Experiments on ISCAS'89/ITC'99 benchmark circuits and a real industry circuit based on 20nm technology with silicon results show that, the proposed DLA Scan Chain stitching method effectively improves the resolution, with negligible impact on chip performance, embedded Scan compaction, transition fault coverage, and test power dissipation. The silicon results even show 7X average resolution improvement comparing to without using the proposed method.
Wutung Cheng - One of the best experts on this subject based on the ideXlab platform.
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diagnosis of intermittent Scan Chain faults through a multistage neural network reasoning process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2020Co-Authors: Mason Chern, Yu Huang, Shihwei Lee, Shiyu Huang, Gaurav Veda, Kunhan Tsai, Wutung ChengAbstract:Diagnosis of intermittent Scan Chain failures still remains a hard problem. In this article, we demonstrate that the use of artificial neural networks (ANNs) can lead to significantly higher accuracy. The key of this method is a multistage process incorporating ANNs with gradually refined focuses. During this process, the final fault suspect is elected through multiple rounds of ANN inference, instead of just one round. At each stage, identification of a proper Affine Group , used as the “candidate set of Scan cells for the next round of ANN inference,” will influence the final diagnostic accuracy. Thus, we propose a validation-based learning procedure for Affine Group derivation to further boost the final diagnostic accuracy. The experimental results on benchmark circuits have shown that this method is, on the average, 17.46% more accurate than a state-of-the-art commercial tool for intermittent stuck-at-0 faults.
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Scan Chain diagnosis based on unsupervised machine learning
Asian Test Symposium, 2017Co-Authors: Yu Huang, B Benware, Randy Klingenberg, Huaxing Tang, Jayant Dsouza, Wutung ChengAbstract:Scan-based testing has proven to be a cost-effective method for achieving good test coverage in digital circuits. It was reported in prior papers that about 30% to 50% of all failing die were due to defects that cause Scan Chains to fail [1][2]. Therefore, Scan Chain failure diagnosis is very important to improve yield. The previously proposed methods of Chain diagnosis were primarily based on either deterministic fault models and simulation algorithms or probabilistic analysis. To handle hard-to-model defect behaviors more robustly, in this paper, we propose a new Scan Chain diagnosis algorithm based on unsupervised machine learning. Its application on "Scannable memory designs" (SMD) is demonstrated to illustrate the effectiveness of the proposed algorithm.
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diagnosis and layout aware dla Scan Chain stitching
IEEE Transactions on Very Large Scale Integration Systems, 2015Co-Authors: Yu Huang, Wutung Cheng, Ruifeng Guo, Liyang Lai, Tingpu Tai, Weipin Changchien, Dawming Lee, Jijan Chen, Sandeep C Eruvathi, Kartik K KumaraAbstract:Without appropriate stitching of Scan Chains, even with good diagnosis algorithm and diagnostic pattern generation, the Chain diagnostic resolution may still be bad. In this paper, we propose a novel pattern-independent diagnosis and layout aware (DLA) Scan Chain stitching method: 1) the resolution is improved by increasing and properly distributing the sensitive Scan cells, which can capture useful diagnostic information under both single- and multiple-fault situations; and 2) the Scan cell layout placement is taken into account to reduce routing overhead and hence preserve the chip performance. Experiments using two different techniques to diagnose ISCAS'89/ITC'99 benchmark circuits with/without embedded Scan compaction show the effectiveness of the proposed method in improving the diagnostic resolution. Impacts on chip performance, embedded Scan compaction, transition fault coverage, and test power dissipation are negligible. The proposed method is also successfully applied to an industry circuit manufactured with 20-nm technology. The silicon results show $7\times$ average resolution improvement comparing to without using the DLA Scan Chain stitching.
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diagnosis and layout aware dla Scan Chain stitching
International Test Conference, 2013Co-Authors: Yu Huang, Wutung Cheng, Ruifeng Guo, Liyang Lai, Tingpu Tai, Weipin Changchien, Dawming Lee, Jijan Chen, Sandeep C Eruvathi, Kartik K KumaraAbstract:Without appropriate stitching of Scan Chains, even with good diagnosis algorithm and diagnostic pattern generation, it may still result in bad Scan Chain diagnostic resolution. To improve the diagnostic resolution, we propose a novel Diagnosis and Layout Aware (DLA) Scan Chain stitching method, which is pattern independent and supports embedded Scan compaction. It is based on three ideas: (1) increasing the number of sensitive Scan cells, which can capture useful diagnostic information; (2) properly distributing the sensitive Scan cells along the Scan Chains to enhance the overall resolution; (3) stitching Scan cells based on their placement at layout to preserve the chip performance. Experiments on ISCAS'89/ITC'99 benchmark circuits and a real industry circuit based on 20nm technology with silicon results show that, the proposed DLA Scan Chain stitching method effectively improves the resolution, with negligible impact on chip performance, embedded Scan compaction, transition fault coverage, and test power dissipation. The silicon results even show 7X average resolution improvement comparing to without using the proposed method.
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distributed dynamic partitioning based diagnosis of Scan Chain
VLSI Test Symposium, 2013Co-Authors: Yu Huang, B Benware, Huaxing Tang, Wutung Cheng, Xiaoxin Fan, Manish Sharma, S M ReddyAbstract:Diagnosis memory footprint for large designs is growing as design sizes grow such that the diagnosis throughput for given computational resources becomes a bottleneck in volume diagnosis. In this paper, we propose a Scan Chain diagnosis flow based on dynamic design partitioning and distributed diagnosis architecture that can improve the diagnosis throughput over one order of magnitude.
Debdeep Mukhopadhyay - One of the best experts on this subject based on the ideXlab platform.
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Scan based side channel attacks on stream ciphers and their counter measures
International Conference on Cryptology in India, 2008Co-Authors: Mukesh Agrawal, Sandip Karmakar, Dhiman Saha, Debdeep MukhopadhyayAbstract:Scan Chain based attacks are a kind of side channel attack, which targets one of the most important feature of today's hardware - the test circuitry. Design for Testability (DFT) is a design technique that adds certain testability features to a hardware design. On the other hand, this very feature opens up a side channel for cryptanalysis, rendering crypto-devices vulnerable to Scan-based attack. Our work studies Scan attack as a general threat to stream ciphers and arrives at a general relation between the design of stream ciphers and their vulnerability to Scan attack. Finally, we propose a scheme which we show to thwart the attacks and is more secure than other contemporary strategies.
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secured flipped Scan Chain model for crypto architecture
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2007Co-Authors: G Sengar, Debdeep Mukhopadhyay, Dipanwita Roy ChowdhuryAbstract:Scan Chains are exploited to develop attacks on cryptographic hardware and steal intellectual properties from the chip. This paper proposes a secured strategy to test designs by inserting a certain number of inverters between randomly selected Scan cells. The security of the scheme has been analyzed. Two detailed case studies of RC4 stream cipher and AES block cipher have been presented to show that the proposed strategy prevents existing Scan-based attacks in the literature. The elegance of the scheme lies in its less hardware overhead.
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cryptoScan a secured Scan Chain architecture
Asian Test Symposium, 2005Co-Authors: Debdeep Mukhopadhyay, S Banerjee, Dipanwita Roychowdhury, Bhargab B BhattacharyaAbstract:Scan based testing is a powerful and popular test technique. However the Scan Chain can be used by an attacker to decipher the cryptogram. The present paper shows such a side-channel attack on LFSR-based stream ciphers using Scan Chains. The paper subsequently discusses a strategy to build the Scan Chains in a tree based pattern with a selfchecking compactor. It has been shown that such a structure prevents such Scan based attacks but does not compromise on fault coverage.
Sungho Kang - One of the best experts on this subject based on the ideXlab platform.
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Scan Chain fault diagnosis using regressions in cryptographic chips for wireless sensor networks
Sensors, 2020Co-Authors: Hyunyul Lim, Minho Cheong, Sungho KangAbstract:Scan structures, which are widely used in cryptographic circuits for wireless sensor networks applications, are essential for testing very-large-scale integration (VLSI) circuits. Faults in cryptographic circuits can be effectively screened out by improving testability and test coverage using a Scan structure. Additionally, Scan testing contributes to yield improvement by identifying fault locations. However, faults in circuits cannot be tested when a fault occurs in the Scan structure. Moreover, various defects occurring early in the manufacturing process are expressed as faults of Scan Chains. Therefore, Scan-Chain diagnosis is crucial. However, it is difficult to obtain a sufficiently high diagnosis resolution and accuracy through the conventional Scan-Chain diagnosis. Therefore, this article proposes a novel Scan-Chain diagnosis method using regression and fan-in and fan-out filters that require shorter training and diagnosis times than existing Scan-Chain diagnoses do. The fan-in and fan-out filters, generated using a circuit logic structure, can highlight important features and remove unnecessary features from raw failure vectors, thereby converting the raw failure vectors to fan-in and fan-out vectors without compromising the diagnosis accuracy. Experimental results confirm that the proposed Scan-Chain-diagnosis method can efficiently provide higher resolutions and accuracies with shorter training and diagnosis times.
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Scan Chain reordering aware x filling and stitching for Scan shift power reduction
Asian Test Symposium, 2015Co-Authors: Sungyoul Seo, Yong Lee, Hyeonchan Lim, Joohwan Lee, Hongbom Yoo, Yojoung Kim, Sungho KangAbstract:As a Scan-based testing enables higher test coverage and faster test time than alternative ways, it is widely used by most system-on-chip (SoC) designers. However, since the number of logic gates is over one hundred million gates, a number of Scan cells lead to excessive power consumption and it produces a low shifting frequency during the Scan shifting mode. In this paper, we present a new Scan shift power reduction method based on a Scan Chain reordering (SR)-aware X-filling and a stitching method. There is no need to require an additional logic for reducing the Scan shift power, just a little routing overhead. Experimental results show that this method improves Scan shift power consumption on benchmark circuits in most cases compared to the results of the previous works.
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a selective Scan Chain activation technique for minimizing average and peak power consumption
IEICE Transactions on Information and Systems, 2010Co-Authors: Jaeseok Park, Sungho KangAbstract:SUMMARY In this paper, we present an efficient low power Scan test technique which simultaneously reduces both average and peak power consumption. The selective Scan Chain activation scheme removes unnecessary Scan Chain utilization during the Scan shift and capture operations. Statistical Scan cell reordering enables efficient Scan Chain removal. The experimental results demonstrated that the proposed method constantly reduces the average and peak power consumption during Scan testing.
Alex Orailoglu - One of the best experts on this subject based on the ideXlab platform.
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fast and energy frugal deterministic test through efficient compression and compaction techniques
Journal of Systems Architecture, 2004Co-Authors: Ozgur Sinanoglu, Alex OrailogluAbstract:Conversion of the flip-flops of the circuit into Scan cells helps ease the test challenge; yet test application time is increased as serial shift operations are employed. Furthermore, the transitions that occur in the Scan Chains during these shifts reflect into significant levels of circuit switching unnecessarily, increasing the power dissipated. Judicious encoding of the correlation among the test vectors and construction of a test vector through predecessor updates helps reduce not only test application time but also Scan Chain transitions as well. Such an encoding scheme, which additionally reduces test data volume, can be further enhanced through appropriately ordering and padding of the test cubes given. The experimental results confirm the significant reductions in test application time, test data volume and test power achieved by the proposed compression methodology.
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test application time and volume compression through seed overlapping
Design Automation Conference, 2003Co-Authors: Wenjing Rao, I Bayraktaroglu, Alex OrailogluAbstract:We propose in this paper an extension on the Scan Chain Concealment technique to further reduce test time and volume requirement. The proposed methodology stems from the architecture of the existing SCC scheme, while it attempts to overlap consecutive test vector seeds, thus providing increased flexibility in exploiting effectively the large volume of don't-care bits in test vectors. We also introduce modified ATPG algorithms upon the previous SCC scheme and explore various implementation strategies. Experimental data exhibit significant reductions on test time and volume over all current test compression techniques.
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test power reduction through minimization of Scan Chain transitions
VLSI Test Symposium, 2002Co-Authors: Ozgur Sinanoglu, I Bayraktaroglu, Alex OrailogluAbstract:Parallel test application helps reduce the otherwise considerable test times in SOCs; yet its applicability is limited by average and peak power considerations. The typical test vector loading techniques result infrequent transitions in the Scan Chain, which in turn reflect into significant levels of circuit switching unnecessarily. Judicious utilization of logic in the Scan Chain can help reduce transitions while loading the test vector needed. No performance degradation ensues as Scan Chain modifications have no impact on functional execution. A computationally efficient scheme is proposed to identify, the location and type of the logic to be inserted. The experimental results confirm the significant reductions in test power possible under the proposed scheme.
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test volume and application time reduction through Scan Chain concealment
Design Automation Conference, 2001Co-Authors: I Bayraktaroglu, Alex OrailogluAbstract:A test pattern compression scheme is proposed in order to reduce test data volume and application time. The number of Scan Chains that can be supported by an ATE is significantly increased by utilizing an on-chip decompressor. The functionality of the ATE is kept intact by moving the decompression task to the circuit under test. While the number of virtual Scan Chains visible to the ATE is kept small, the number of internal Scan Chains driven by the decompressed pattern sequence can be sinificantly increased.
