The Experts below are selected from a list of 10479 Experts worldwide ranked by ideXlab platform

Ahmed Louri - One of the best experts on this subject based on the ideXlab platform.

  • Scalable optical interconnection network for parallel and distributed computing
    Adaptive Optics: Analysis and Methods Computational Optical Sensing and Imaging Information Photonics Signal Recovery and Synthesis Topical Meetings o, 2005
    Co-Authors: Avinash Kodi, Ahmed Louri
    Abstract:

    In this paper, a high-performance, scalable, parallel computing system called RAPID is designed using switchless, passive optical interconnect technology. RAPID outperforms current electrical multiprocessor systems by significantly decreasing the remote Memory Access Latency.

  • Hot Interconnects - Design of a high-speed optical interconnect for scalable shared Memory multiprocessors
    IEEE Micro, 2005
    Co-Authors: Avinash Kodi, Ahmed Louri
    Abstract:

    The paper proposes a highly connected optical interconnect based architecture that maximizes the channel availability for future scalable parallel computers, such as distributed shared Memory (DSM) multiprocessors and cluster networks. As the system size increases, various messages (requests, responses and acknowledgments) increase in the network resulting in contention. This results in increasing the remote Memory Access Latency and significantly affects the performance of these parallel computers. As a solution, we propose an architecture called RAPID (reconfigurable and scalable all-photonic interconnect for distributed-shared Memory), that provides low remote Memory Access Latency by providing fast and efficient unicast, multicast and broadcast capabilities using a combination of aggressively designed WDM, TDM and SDM techniques. We evaluated RAPID based on network characteristics and by simulation using synthetic traffic workloads and compared it against other networks such as electrical ring, torus, mesh and hypercube networks. We found that RAPID outperforms all networks and satisfies most of the requirements of parallel computer design such as low Latency, high bandwidth, high connectivity, and easy scalability.

  • design of a high speed optical interconnect for scalable shared Memory multiprocessors
    High Performance Interconnects, 2004
    Co-Authors: Avinash Kodi, Ahmed Louri
    Abstract:

    The paper proposes a highly connected optical interconnect based architecture that maximizes the channel availability for future scalable parallel computers, such as distributed shared Memory (DSM) multiprocessors and cluster networks. As the system size increases, various messages (requests, responses and acknowledgments) increase in the network resulting in contention. This results in increasing the remote Memory Access Latency and significantly affects the performance of these parallel computers. As a solution, we propose an architecture called RAPID (reconfigurable and scalable all-photonic interconnect for distributed-shared Memory), that provides low remote Memory Access Latency by providing fast and efficient unicast, multicast and broadcast capabilities using a combination of aggressively designed WDM, TDM and SDM techniques. We evaluated RAPID based on network characteristics and by simulation using synthetic traffic workloads and compared it against other networks such as electrical ring, torus, mesh and hypercube networks. We found that RAPID outperforms all networks and satisfies most of the requirements of parallel computer design such as low Latency, high bandwidth, high connectivity, and easy scalability.

  • IPDPS - A scalable architecture for distributed shared Memory multiprocessors using optical interconnects
    18th International Parallel and Distributed Processing Symposium 2004. Proceedings., 1
    Co-Authors: Avinash Kodi, Ahmed Louri
    Abstract:

    Summary form only given. We describe the design and analysis of a scalable architecture suitable for large-scale DSMs (distributed shared Memory) systems. The approach is based on an interconnect technology which combines optical components and a novel architecture design. In DSM systems, as the network size increases, network contention results in increasing the critical remote Memory Access Latency, which significantly penalizes the performance of DSM systems. In our proposed architecture called RAPID (reconfigurable and scalable all-photonic interconnect for distributed-shared Memory), we provide high connectivity by maximizing the channel availability for remote communication to reduce the remote Memory Access Latency. RAPID also provides fast and efficient unicast, multicast and broadcast capabilities using a combination of aggressively designed wavelength, time and space-division multiplexing techniques. We evaluated RAPID based on network characteristics, power budget criteria and simulation using synthetic traffic workloads and compared it against other scalable electrical networks. We found that RAPID, not only outperforms other networks, but also, satisfies most of the requirements of shared Memory multiprocessor design such as low Latency, high bandwidth, high connectivity, and easy scalability.

Lee-sup Kim - One of the best experts on this subject based on the ideXlab platform.

  • HPCA - NUAT: A non-uniform Access time Memory controller
    2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), 2014
    Co-Authors: Wongyu Shin, Jeongmin Yang, Jungwhan Choi, Lee-sup Kim
    Abstract:

    With rapid development of micro-processors, off-chip Memory Access becomes a system bottleneck. DRAM, a main Memory in most computers, has concentrated only on capacity and bandwidth for decades to achieve high performance computing. However, DRAM Access Latency should also be considered to keep the development trend in multi-core era. Therefore, we propose NUAT which is a new Memory controller focusing on reducing Memory Access Latency without any modification of the existing DRAM structure. We only exploit DRAM's intrinsic phenomenon: electric charge variation in DRAM cell capacitors. Given the cost-sensitive DRAM market, it is a big advantage in terms of actual implementation. NUAT gives a score to every Memory Access request and the request with the highest score obtains a priority. For scoring, we introduce two new concepts: Partitioned Bank Rotation (PBR) and PBR Page Mode (PPM). First, PBR is a mechanism that draws information of Access speed from refresh timing and position; the request which has faster Access speed gains higher score. Second, PPM selects a better page mode between open- and close-page modes based on the information from PBR. Evaluations show that NUAT decreases Memory Access Latency significantly for various environments.

Wongyu Shin - One of the best experts on this subject based on the ideXlab platform.

  • nuat a non uniform Access time Memory controller
    High-Performance Computer Architecture, 2014
    Co-Authors: Wongyu Shin, Jeongmin Yang, Jungwhan Choi
    Abstract:

    With rapid development of micro-processors, off-chip Memory Access becomes a system bottleneck. DRAM, a main Memory in most computers, has concentrated only on capacity and bandwidth for decades to achieve high performance computing. However, DRAM Access Latency should also be considered to keep the development trend in multi-core era. Therefore, we propose NUAT which is a new Memory controller focusing on reducing Memory Access Latency without any modification of the existing DRAM structure. We only exploit DRAM's intrinsic phenomenon: electric charge variation in DRAM cell capacitors. Given the cost-sensitive DRAM market, it is a big advantage in terms of actual implementation. NUAT gives a score to every Memory Access request and the request with the highest score obtains a priority. For scoring, we introduce two new concepts: Partitioned Bank Rotation (PBR) and PBR Page Mode (PPM). First, PBR is a mechanism that draws information of Access speed from refresh timing and position; the request which has faster Access speed gains higher score. Second, PPM selects a better page mode between open- and close-page modes based on the information from PBR. Evaluations show that NUAT decreases Memory Access Latency significantly for various environments.

  • nuat a non uniform Access time Memory controller
    High-Performance Computer Architecture, 2014
    Co-Authors: Wongyu Shin, Jeongmin Yang, Jungwhan Choi
    Abstract:

    With rapid development of micro-processors, off-chip Memory Access becomes a system bottleneck. DRAM, a main Memory in most computers, has concentrated only on capacity and bandwidth for decades to achieve high performance computing. However, DRAM Access Latency should also be considered to keep the development trend in multi-core era. Therefore, we propose NUAT which is a new Memory controller focusing on reducing Memory Access Latency without any modification of the existing DRAM structure. We only exploit DRAM's intrinsic phenomenon: electric charge variation in DRAM cell capacitors. Given the cost-sensitive DRAM market, it is a big advantage in terms of actual implementation. NUAT gives a score to every Memory Access request and the request with the highest score obtains a priority. For scoring, we introduce two new concepts: Partitioned Bank Rotation (PBR) and PBR Page Mode (PPM). First, PBR is a mechanism that draws information of Access speed from refresh timing and position; the request which has faster Access speed gains higher score. Second, PPM selects a better page mode between open- and close-page modes based on the information from PBR. Evaluations show that NUAT decreases Memory Access Latency significantly for various environments.

  • HPCA - NUAT: A non-uniform Access time Memory controller
    2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), 2014
    Co-Authors: Wongyu Shin, Jeongmin Yang, Jungwhan Choi, Lee-sup Kim
    Abstract:

    With rapid development of micro-processors, off-chip Memory Access becomes a system bottleneck. DRAM, a main Memory in most computers, has concentrated only on capacity and bandwidth for decades to achieve high performance computing. However, DRAM Access Latency should also be considered to keep the development trend in multi-core era. Therefore, we propose NUAT which is a new Memory controller focusing on reducing Memory Access Latency without any modification of the existing DRAM structure. We only exploit DRAM's intrinsic phenomenon: electric charge variation in DRAM cell capacitors. Given the cost-sensitive DRAM market, it is a big advantage in terms of actual implementation. NUAT gives a score to every Memory Access request and the request with the highest score obtains a priority. For scoring, we introduce two new concepts: Partitioned Bank Rotation (PBR) and PBR Page Mode (PPM). First, PBR is a mechanism that draws information of Access speed from refresh timing and position; the request which has faster Access speed gains higher score. Second, PPM selects a better page mode between open- and close-page modes based on the information from PBR. Evaluations show that NUAT decreases Memory Access Latency significantly for various environments.

Jungwhan Choi - One of the best experts on this subject based on the ideXlab platform.

  • nuat a non uniform Access time Memory controller
    High-Performance Computer Architecture, 2014
    Co-Authors: Wongyu Shin, Jeongmin Yang, Jungwhan Choi
    Abstract:

    With rapid development of micro-processors, off-chip Memory Access becomes a system bottleneck. DRAM, a main Memory in most computers, has concentrated only on capacity and bandwidth for decades to achieve high performance computing. However, DRAM Access Latency should also be considered to keep the development trend in multi-core era. Therefore, we propose NUAT which is a new Memory controller focusing on reducing Memory Access Latency without any modification of the existing DRAM structure. We only exploit DRAM's intrinsic phenomenon: electric charge variation in DRAM cell capacitors. Given the cost-sensitive DRAM market, it is a big advantage in terms of actual implementation. NUAT gives a score to every Memory Access request and the request with the highest score obtains a priority. For scoring, we introduce two new concepts: Partitioned Bank Rotation (PBR) and PBR Page Mode (PPM). First, PBR is a mechanism that draws information of Access speed from refresh timing and position; the request which has faster Access speed gains higher score. Second, PPM selects a better page mode between open- and close-page modes based on the information from PBR. Evaluations show that NUAT decreases Memory Access Latency significantly for various environments.

  • nuat a non uniform Access time Memory controller
    High-Performance Computer Architecture, 2014
    Co-Authors: Wongyu Shin, Jeongmin Yang, Jungwhan Choi
    Abstract:

    With rapid development of micro-processors, off-chip Memory Access becomes a system bottleneck. DRAM, a main Memory in most computers, has concentrated only on capacity and bandwidth for decades to achieve high performance computing. However, DRAM Access Latency should also be considered to keep the development trend in multi-core era. Therefore, we propose NUAT which is a new Memory controller focusing on reducing Memory Access Latency without any modification of the existing DRAM structure. We only exploit DRAM's intrinsic phenomenon: electric charge variation in DRAM cell capacitors. Given the cost-sensitive DRAM market, it is a big advantage in terms of actual implementation. NUAT gives a score to every Memory Access request and the request with the highest score obtains a priority. For scoring, we introduce two new concepts: Partitioned Bank Rotation (PBR) and PBR Page Mode (PPM). First, PBR is a mechanism that draws information of Access speed from refresh timing and position; the request which has faster Access speed gains higher score. Second, PPM selects a better page mode between open- and close-page modes based on the information from PBR. Evaluations show that NUAT decreases Memory Access Latency significantly for various environments.

  • HPCA - NUAT: A non-uniform Access time Memory controller
    2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), 2014
    Co-Authors: Wongyu Shin, Jeongmin Yang, Jungwhan Choi, Lee-sup Kim
    Abstract:

    With rapid development of micro-processors, off-chip Memory Access becomes a system bottleneck. DRAM, a main Memory in most computers, has concentrated only on capacity and bandwidth for decades to achieve high performance computing. However, DRAM Access Latency should also be considered to keep the development trend in multi-core era. Therefore, we propose NUAT which is a new Memory controller focusing on reducing Memory Access Latency without any modification of the existing DRAM structure. We only exploit DRAM's intrinsic phenomenon: electric charge variation in DRAM cell capacitors. Given the cost-sensitive DRAM market, it is a big advantage in terms of actual implementation. NUAT gives a score to every Memory Access request and the request with the highest score obtains a priority. For scoring, we introduce two new concepts: Partitioned Bank Rotation (PBR) and PBR Page Mode (PPM). First, PBR is a mechanism that draws information of Access speed from refresh timing and position; the request which has faster Access speed gains higher score. Second, PPM selects a better page mode between open- and close-page modes based on the information from PBR. Evaluations show that NUAT decreases Memory Access Latency significantly for various environments.

Avinash Kodi - One of the best experts on this subject based on the ideXlab platform.

  • Scalable optical interconnection network for parallel and distributed computing
    Adaptive Optics: Analysis and Methods Computational Optical Sensing and Imaging Information Photonics Signal Recovery and Synthesis Topical Meetings o, 2005
    Co-Authors: Avinash Kodi, Ahmed Louri
    Abstract:

    In this paper, a high-performance, scalable, parallel computing system called RAPID is designed using switchless, passive optical interconnect technology. RAPID outperforms current electrical multiprocessor systems by significantly decreasing the remote Memory Access Latency.

  • Hot Interconnects - Design of a high-speed optical interconnect for scalable shared Memory multiprocessors
    IEEE Micro, 2005
    Co-Authors: Avinash Kodi, Ahmed Louri
    Abstract:

    The paper proposes a highly connected optical interconnect based architecture that maximizes the channel availability for future scalable parallel computers, such as distributed shared Memory (DSM) multiprocessors and cluster networks. As the system size increases, various messages (requests, responses and acknowledgments) increase in the network resulting in contention. This results in increasing the remote Memory Access Latency and significantly affects the performance of these parallel computers. As a solution, we propose an architecture called RAPID (reconfigurable and scalable all-photonic interconnect for distributed-shared Memory), that provides low remote Memory Access Latency by providing fast and efficient unicast, multicast and broadcast capabilities using a combination of aggressively designed WDM, TDM and SDM techniques. We evaluated RAPID based on network characteristics and by simulation using synthetic traffic workloads and compared it against other networks such as electrical ring, torus, mesh and hypercube networks. We found that RAPID outperforms all networks and satisfies most of the requirements of parallel computer design such as low Latency, high bandwidth, high connectivity, and easy scalability.

  • design of a high speed optical interconnect for scalable shared Memory multiprocessors
    High Performance Interconnects, 2004
    Co-Authors: Avinash Kodi, Ahmed Louri
    Abstract:

    The paper proposes a highly connected optical interconnect based architecture that maximizes the channel availability for future scalable parallel computers, such as distributed shared Memory (DSM) multiprocessors and cluster networks. As the system size increases, various messages (requests, responses and acknowledgments) increase in the network resulting in contention. This results in increasing the remote Memory Access Latency and significantly affects the performance of these parallel computers. As a solution, we propose an architecture called RAPID (reconfigurable and scalable all-photonic interconnect for distributed-shared Memory), that provides low remote Memory Access Latency by providing fast and efficient unicast, multicast and broadcast capabilities using a combination of aggressively designed WDM, TDM and SDM techniques. We evaluated RAPID based on network characteristics and by simulation using synthetic traffic workloads and compared it against other networks such as electrical ring, torus, mesh and hypercube networks. We found that RAPID outperforms all networks and satisfies most of the requirements of parallel computer design such as low Latency, high bandwidth, high connectivity, and easy scalability.

  • IPDPS - A scalable architecture for distributed shared Memory multiprocessors using optical interconnects
    18th International Parallel and Distributed Processing Symposium 2004. Proceedings., 1
    Co-Authors: Avinash Kodi, Ahmed Louri
    Abstract:

    Summary form only given. We describe the design and analysis of a scalable architecture suitable for large-scale DSMs (distributed shared Memory) systems. The approach is based on an interconnect technology which combines optical components and a novel architecture design. In DSM systems, as the network size increases, network contention results in increasing the critical remote Memory Access Latency, which significantly penalizes the performance of DSM systems. In our proposed architecture called RAPID (reconfigurable and scalable all-photonic interconnect for distributed-shared Memory), we provide high connectivity by maximizing the channel availability for remote communication to reduce the remote Memory Access Latency. RAPID also provides fast and efficient unicast, multicast and broadcast capabilities using a combination of aggressively designed wavelength, time and space-division multiplexing techniques. We evaluated RAPID based on network characteristics, power budget criteria and simulation using synthetic traffic workloads and compared it against other scalable electrical networks. We found that RAPID, not only outperforms other networks, but also, satisfies most of the requirements of shared Memory multiprocessor design such as low Latency, high bandwidth, high connectivity, and easy scalability.